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Simplify PCI code #5426

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1 change: 0 additions & 1 deletion Cargo.lock
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1 change: 0 additions & 1 deletion src/pci/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@ libc = "0.2.175"
log = "0.4.27"
serde = { version = "1.0.219", features = ["derive"] }
thiserror = "2.0.16"
vm-allocator = "0.1.3"
vm-device = { path = "../vm-device" }
vm-memory = { version = "0.16.1", features = [
"backend-mmap",
Expand Down
36 changes: 17 additions & 19 deletions src/pci/src/bus.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -213,7 +213,6 @@ impl PciConfigIo {
params.new_base,
params.len,
device.deref_mut(),
params.region_type,
) {
error!(
"Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
Expand Down Expand Up @@ -348,7 +347,6 @@ impl PciConfigMmio {
params.new_base,
params.len,
device.deref_mut(),
params.region_type,
) {
error!(
"Failed moving device BAR: {}: 0x{:x}->0x{:x}(0x{:x})",
Expand Down Expand Up @@ -445,8 +443,8 @@ mod tests {
use super::{PciBus, PciConfigIo, PciConfigMmio, PciRoot};
use crate::bus::{DEVICE_ID_INTEL_VIRT_PCIE_HOST, VENDOR_ID_INTEL};
use crate::{
DeviceRelocation, PciBarConfiguration, PciBarPrefetchable, PciBarRegionType, PciClassCode,
PciConfiguration, PciDevice, PciHeaderType, PciMassStorageSubclass,
DeviceRelocation, PciClassCode, PciConfiguration, PciDevice, PciHeaderType,
PciMassStorageSubclass,
};

#[derive(Debug, Default)]
Expand All @@ -467,7 +465,6 @@ mod tests {
_new_base: u64,
_len: u64,
_pci_dev: &mut dyn crate::PciDevice,
_region_type: crate::PciBarRegionType,
) -> std::result::Result<(), std::io::Error> {
self.reloc_cnt
.fetch_add(1, std::sync::atomic::Ordering::SeqCst);
Expand All @@ -493,15 +490,7 @@ mod tests {
None,
);

config
.add_pci_bar(&PciBarConfiguration {
addr: 0x1000,
size: 0x1000,
idx: 0,
region_type: PciBarRegionType::Memory32BitRegion,
prefetchable: PciBarPrefetchable::Prefetchable,
})
.unwrap();
config.add_pci_bar(0, 0x1000, 0x1000);

PciDevMock(config)
}
Expand Down Expand Up @@ -920,23 +909,32 @@ mod tests {
read_mmio_config(&mut mmio_config, 0, 1, 0, 0x4, 0, &mut buffer);
let old_addr = u32::from_le_bytes(buffer) & 0xffff_fff0;
assert_eq!(old_addr, 0x1000);

// Writing the lower 32bits first should not trigger any reprogramming
write_mmio_config(
&mut mmio_config,
0,
1,
0,
0x4,
0,
&u32::to_le_bytes(0x1312_1110),
&u32::to_le_bytes(0x1312_0000),
);

read_mmio_config(&mut mmio_config, 0, 1, 0, 0x4, 0, &mut buffer);
let new_addr = u32::from_le_bytes(buffer) & 0xffff_fff0;
assert_eq!(new_addr, 0x1312_1110);
assert_eq!(mock.cnt(), 1);
assert_eq!(new_addr, 0x1312_0000);
assert_eq!(mock.cnt(), 0);

// BAR1 should not be used, so reading its address should return all 0s
// Writing the upper 32bits first should now trigger the reprogramming logic
write_mmio_config(&mut mmio_config, 0, 1, 0, 0x5, 0, &u32::to_le_bytes(0x1110));
read_mmio_config(&mut mmio_config, 0, 1, 0, 0x5, 0, &mut buffer);
let new_addr = u32::from_le_bytes(buffer);
assert_eq!(new_addr, 0x1110);
assert_eq!(mock.cnt(), 1);

// BAR2 should not be used, so reading its address should return all 0s
read_mmio_config(&mut mmio_config, 0, 1, 0, 0x6, 0, &mut buffer);
assert_eq!(buffer, [0x0, 0x0, 0x0, 0x0]);

// and reprogramming shouldn't have any effect
Expand All @@ -950,7 +948,7 @@ mod tests {
&u32::to_le_bytes(0x1312_1110),
);

read_mmio_config(&mut mmio_config, 0, 1, 0, 0x5, 0, &mut buffer);
read_mmio_config(&mut mmio_config, 0, 1, 0, 0x6, 0, &mut buffer);
assert_eq!(buffer, [0x0, 0x0, 0x0, 0x0]);
}
}
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