fix: BAR writes through PCI configuration capability #5403

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Merged

bchalios merged 1 commit into firecracker-microvm:main from bchalios:fix_pci_config_cap_writes

Aug 26, 2025

Merged

fix: BAR writes through PCI configuration capability #5403

bchalios merged 1 commit into firecracker-microvm:main from bchalios:fix_pci_config_cap_writes

Aug 26, 2025

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bchalios

@bchalios


 fix: BAR writes through PCI configuration capability

35f02a1

PCI configuration capability allows a driver to access a BAR without
mapping it in virtual address space. The driver issues reads/writes
directly within the PCI configuration space (which should always be
addressable either via MMIO or Port IO) which the device translates
corresponding BAR accesses.
The way this works is that the guests writes the offset and length of a
BAR access within the capability structure and then reads/writes data
using a 4-bytes dedicated array that also lives in the capability
address space.
We had a bug in the logic that handles writes where a guest would
program a write of a certain length (L) and then try to perform a write
using a buffer where buffer.len() < L. Our logic would then try to
perform a write using the slice buffer[..L] which would cause Rust to
panic with an out of range exception.
Fix this by taking into account the buffer's length and using a slice
with length min(L, buffer.len()).
Signed-off-by: Babis Chalios <bchalios@amazon.es>

@bchalios bchalios enabled auto-merge (rebase)

August 25, 2025 14:38

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codecov bot commented Aug 25, 2025 •

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 83.17%. Comparing base (92e936d) to head (35f02a1).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files

@@ Coverage Diff @@
## main #5403 +/- ##
==========================================
+ Coverage 83.12% 83.17% +0.04% 
==========================================
 Files 266 266 
 Lines 30526 30527 +1 
==========================================
+ Hits 25376 25391 +15 
+ Misses 5150 5136 -14

Flag	Coverage Δ
5.10-c5n.metal	`83.23% <100.00%> (+<0.01%)`	⬆️
5.10-m5n.metal	`83.23% <100.00%> (+<0.01%)`	⬆️
5.10-m6a.metal	`82.54% <100.00%> (+<0.01%)`	⬆️
5.10-m6g.metal	`79.86% <100.00%> (+<0.01%)`	⬆️
5.10-m6i.metal	`83.22% <100.00%> (-0.01%)`	⬇️
5.10-m7a.metal-48xl	`82.53% <100.00%> (?)`
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5.10-m8g.metal-48xl	`79.86% <100.00%> (?)`
6.1-c5n.metal	`83.27% <100.00%> (+<0.01%)`	⬆️
6.1-m5n.metal	`83.27% <100.00%> (-0.01%)`	⬇️
6.1-m6a.metal	`82.58% <100.00%> (+<0.01%)`	⬆️
6.1-m6g.metal	`79.86% <100.00%> (+<0.01%)`	⬆️
6.1-m6i.metal	`83.26% <100.00%> (+<0.01%)`	⬆️
6.1-m7a.metal-48xl	`82.58% <100.00%> (?)`
6.1-m7g.metal	`79.86% <100.00%> (+<0.01%)`	⬆️
6.1-m7i.metal-24xl	`83.29% <100.00%> (?)`
6.1-m7i.metal-48xl	`83.28% <100.00%> (?)`
6.1-m8g.metal-24xl	`79.86% <100.00%> (?)`
6.1-m8g.metal-48xl	`79.86% <100.00%> (?)`