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CPU 6507

DoubleGate edited this page Jul 8, 2026 · 1 revision

MOS 6507 CPU

What the 6507 is

The 6507 is a MOS 6502 die in a 28-pin DIP. The package drops the 6502's A13–A15 pins (leaving A0–A12, a 13-bit / 8 KiB address bus) and omits both the IRQ and NMI pins — those lines were sacrificed to make room for A12. The 6507 and 6502 share the same underlying silicon and differ only in the final metallization layer, so for emulation the 6507 core is a 6502 core: same registers, same documented and undocumented NMOS instructions, same NMOS decimal mode.

Registers / state

The Cpu register file:

Field Width Notes
a 8 accumulator
x, y 8 index registers
sp 8 stack pointer; the 0100ドル stack page maps into the RIOT's 128-byte RAM mirror
pc 16 program counter (only A0–A12 reach the bus)
p (Status) 8 C Z I D B U V N; bit 5 (U) always reads 1, B exists only in the pushed copy
cycles 64 total CPU cycles since power-on (used by the golden-log differ)

Power-on register values (A/X/Y — reset does not touch these) are randomized from the seeded PRNG in the owning System, never the OS RNG — see Architecture-Decision-Records ADR 0004 (determinism) and ADR 0006 (power-on seeding).

Consequences of the 6507 packaging

No hardware interrupts. There is no IRQ/NMI dispatch path — see Lockstep-Scheduler § No interrupt dispatch. The BRK opcode and the RESET vector ($FFFC/$FFFD) still work; the IRQ/BRK vector ($FFFE/$FFFF) is read on BRK but never fired by hardware. The only timing mechanisms available to a 2600 program are polling the RIOT's interval timer (see RIOT) or WSYNC (see TIA).

Because there is no interrupt controller to model, the 6507 core in Rusty2600 is, in practice, a plain 6502 execution engine: full documented instruction set, the classic undocumented NMOS opcodes, and cycle-accurate addressing-mode timing (including the read-modify-write double-access pattern and branch cycle-counting), with the IRQ/NMI dispatch machinery simply absent rather than stubbed out.

Accuracy verification

The CPU core is verified against two independent oracles, not just self-consistency:

  • The Klaus Dormann 6502_functional_test and 6502_decimal_test (Bruce Clark BCD) suites, run to completion via a shared sentinel-trap runner.
  • The SingleStepTests/ProcessorTests 6502 corpus — per-opcode, per-cycle bus-activity vectors covering NMOS behavior including undocumented opcodes. Rusty2600 passes 4,660/4,660 trimmed cases across all 233 opcodes, with the full ~10,000-case-per-opcode corpus re-verified weekly in CI.
  • A genuine externally-oracled golden trace: the first 20,000 retired instructions of the Klaus functional test, captured independently from Gopher2600's own Go CPU implementation and diffed register-for-register, cycle-for-cycle against Rusty2600's own execution. Two independently-implemented 6502 cores agreeing this closely is real external validation, distinct from a test ROM's own internal pass/fail self-check.

See Testing-Strategy for how these layers fit into the full accuracy battery.

See also

Architecture-Overview · Lockstep-Scheduler · RIOT · Testing-Strategy

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