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Commit 2bd3185

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dmidecode: Add support for large cache sizes
Add support for the "Maximum Cache Size 2" and "Installed Cache Size 2" fields introduced in SMBIOS specification version 3.1.0. Signed-off-by: Jean Delvare <jdelvare@suse.de>
1 parent a8a2ade commit 2bd3185

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‎CHANGELOG‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
(DMI type 4).
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* dmidecode.c: Decode the MIDR register on ARM processors
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(DMI type 4).
13+
* dmidecode.c: Add support for large cache sizes (DMI type 7).
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2017年04月11日 Jean Delvare <jdelvare@suse.de>
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‎dmidecode.c‎

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1536,6 +1536,21 @@ static void dmi_cache_size(u16 code)
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printf(" %u kB", code);
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}
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1539+
static void dmi_cache_size_2(u32 code)
1540+
{
1541+
if (code & 0x80000000)
1542+
{
1543+
code &= 0x7FFFFFFFLU;
1544+
/* Use a more convenient unit for large cache size */
1545+
if (code >= 0x8000)
1546+
printf(" %u MB", code >> 4);
1547+
else
1548+
printf(" %u kB", code << 6);
1549+
}
1550+
else
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printf(" %u kB", code);
1552+
}
1553+
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static void dmi_cache_types(u16 code, const char *sep)
15401555
{
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/* 7.8.2 */
@@ -3576,10 +3591,16 @@ static void dmi_decode(const struct dmi_header *h, u16 ver)
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printf("\tLocation: %s\n",
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dmi_cache_location((WORD(data + 0x05) >> 5) & 0x0003));
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printf("\tInstalled Size:");
3579-
dmi_cache_size(WORD(data + 0x09));
3594+
if (h->length >= 0x1B)
3595+
dmi_cache_size_2(DWORD(data + 0x17));
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else
3597+
dmi_cache_size(WORD(data + 0x09));
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printf("\n");
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printf("\tMaximum Size:");
3582-
dmi_cache_size(WORD(data + 0x07));
3600+
if (h->length >= 0x17)
3601+
dmi_cache_size_2(DWORD(data + 0x13));
3602+
else
3603+
dmi_cache_size(WORD(data + 0x07));
35833604
printf("\n");
35843605
printf("\tSupported SRAM Types:");
35853606
dmi_cache_types(WORD(data + 0x0B), "\n\t\t");

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