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Commit a8a2ade

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dmidecode: Decode the MIDR register on ARM processors
Version 3.1.0 of the SMBIOS specification says that the Processor ID field maps to the MIDR register on ARM processors, decode it. Signed-off-by: Jean Delvare <jdelvare@suse.de>
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‎CHANGELOG‎

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,8 @@
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* dmidecode.c: Add new enumerated values for processors (DMI type 4).
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* dmidecode.c: Don't assume 8-bit processor family in dmi_processor_id
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(DMI type 4).
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* dmidecode.c: Decode the MIDR register on ARM processors
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(DMI type 4).
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2017年04月11日 Jean Delvare <jdelvare@suse.de>
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‎dmidecode.c‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1056,6 +1056,22 @@ static void dmi_processor_id(const struct dmi_header *h, const char *prefix)
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return;
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}
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}
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else if ((type >= 0x100 && type <= 0x101) /* ARM */
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|| (type >= 0x118 && type <= 0x119)) /* ARM */
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{
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u32 midr = DWORD(p);
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/*
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* The format of this field was not defined for ARM processors
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* before version 3.1.0 of the SMBIOS specification, so we
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* silently skip it if it reads all zeroes.
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*/
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if (midr == 0)
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return;
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printf("%sSignature: Implementor 0x%02x, Variant 0x%x, Architecture %u, Part 0x%03x, Revision %u\n",
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prefix, midr >> 24, (midr >> 20) & 0xF,
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(midr >> 16) & 0xF, (midr >> 4) & 0xFFF, midr & 0xF);
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return;
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}
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else if ((type >= 0x0B && type <= 0x15) /* Intel, Cyrix */
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|| (type >= 0x28 && type <= 0x2F) /* Intel */
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|| (type >= 0xA1 && type <= 0xB3) /* Intel */
@@ -1094,7 +1110,7 @@ static void dmi_processor_id(const struct dmi_header *h, const char *prefix)
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else
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return;
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}
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else /* not X86-class */
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else /* neither X86 nor ARM */
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return;
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/*

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