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* >>> MsC Final Project <<<
* @name: FPGA Based Multimedia Player
* @uni: University of York
* @Msc: DSE Programme 2019/20
* @Authors: Bernard Guncic & Oliver Forbes-Shaw
* @Hardware: PYNQ-Z2:-https://www.tul.com.tw/productspynq-z2.html
* HyperPixel 4.0 inch touchscreen:- https://shop.pimoroni.com/products/hyperpixel-4?variant=12569485443155
* @Software: Vivado 2017年4月1日 and its SDK
*
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VIVADO:
- Run create_project.bat file inside /scripts folder
- Vivado project will be generated
- Generate bitstream
- Export Hardware (*include bitstream)
SDK:
- Launch Xilinx SDK from Vivado
- Import project files and BSP from /sw/sdk folder
I2S Slave IP used in this project is developed by Harald-rosenfeldt
https://www.harald-rosenfeldt.de/2018/01/06/zynq-use-audio-codec-with-variable-sampling-rate/