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@PremShah0208
PremShah0208
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Prem Shah PremShah0208

Computer Engineering Graduate | Embedded Systems | Digital Hardware | FPGA/RTL | Hardware Validation

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PremShah0208 /README.md

Hi, I'm Prem Shah πŸ‘‹

Computer Engineering Graduate | Embedded Systems | Digital Hardware | FPGA/RTL | Hardware Validation

I enjoy building, testing, and debugging systems that bring hardware and software together.


πŸ‘¨β€πŸ’» About Me

  • M.S. in Computer Engineering from California State University, Northridge
  • Experience across embedded systems, FPGA/RTL design, hardware validation, and system integration
  • Built hardware-software projects using Raspberry Pi, Embedded Linux, Python, Verilog, and SystemVerilog
  • Comfortable with simulation, debugging, testing, and bringing engineering systems from development through validation

πŸ› οΈ Technical Skills

Python C C++ Verilog SystemVerilog Linux Raspberry Pi Git

Programming: C, C++, Python, Java, SQL

Hardware & RTL: Verilog, SystemVerilog, FPGA, RTL Design, Digital Systems, SoC Design

Embedded Systems: Raspberry Pi, Embedded Linux, Camera Integration, Hardware/Software Integration, System Testing

Verification & Validation: RTL Simulation, Testbench Development, Waveform Debugging, Hardware Validation, System Integration Testing

Tools: Vivado, Xilinx ISE, Synopsys VCS, DVE, Git, Linux, MobaXterm

Data & Machine Learning: TensorFlow, Keras, Machine Learning, Data Analysis


πŸ“Œ Featured Projects

Raspberry Pi Python Embedded Linux Picamera2

Developed a low-cost wearable navigation-support prototype using a Raspberry Pi Zero 2 W, Camera Module V2, Python, and Embedded Linux. Implemented camera-based environmental analysis, audio feedback, calibration, testing, and standalone Linux service operation.


Verilog SystemVerilog Synopsys VCS DVE

Designed and verified a ×ば぀3 fixed-point matrix multiplication system using Verilog and SystemVerilog. Implemented Q-format arithmetic and validated functionality using Synopsys VCS, DVE, testbenches, and waveform debugging.


Verilog Digital Design Pipelining Simulation

Implemented and simulated a 5-stage pipelined processor while exploring datapath design, control logic, instruction execution, and pipeline behavior.


FPGA & SoC Development

FPGA Verilog SystemVerilog Vivado Python

Worked with FPGA and SoC development platforms using Verilog/SystemVerilog, Vivado, Xilinx ISE, simulation, hardware implementation, and Python-based hardware interaction.


Python TensorFlow Keras Transfer Learning Image Classification

Developed a transfer-learning image classification workflow using TensorFlow and Keras with VGG16, ResNet50, and EfficientNetB0 to classify blood-cell images across four classes.


Used Car Price Prediction

R Machine Learning Regression CatBoost Data Analysis

Built and evaluated machine-learning models for vehicle price prediction using large automotive datasets, feature analysis, regression techniques, and model-performance metrics.


πŸ“š Currently Exploring

  • Embedded and firmware development
  • FPGA/RTL design and verification
  • Hardware validation and system integration
  • SoC and digital hardware development
  • C/C++ and Python for engineering applications

🀝 Connect With Me

LinkedIn

Pinned Loading

  1. Assistive-Voice-Glasses Assistive-Voice-Glasses Public

    Low-cost Raspberry Pi-based wearable navigation support system with camera-based obstacle detection and audio feedback.

    Python

  2. Fixed-Point-Matrix-Multiplication Fixed-Point-Matrix-Multiplication Public

    3x3 Q4.4 fixed-point matrix multiplier designed in Verilog and verified using Synopsys VCS and DVE.

    Verilog

  3. 5-Stage-RISC-Pipeline 5-Stage-RISC-Pipeline Public

    5-stage RISC pipeline processor simulation in Verilog with modular CPU components and waveform-based verification.

    Verilog

  4. Leukemia-Blood-Cell-Classification Leukemia-Blood-Cell-Classification Public

    Deep learning classification of peripheral blood smear images using VGG16, ResNet50, and EfficientNetB0 with TensorFlow/Keras.

    Python

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