Bachelor study at FIT VUT Brno
3rd semester - winter 2017
Subject: Design of Computer Systems (INP)
- Overall: 18/23
- CPU implementation: 12/17
| Code | Result |
|---|---|
| ++++++++++ | ok |
| ---------- | ok |
| +>++>+++ | ok |
| <+<++<+++ | ok |
| .+.+.+. | ok |
| ,+,+,+, | ok |
| [........]noLCD[.........] | ok |
| +++[.-] | ok |
| +++++[>++[>+.<-]<-] | error |
| +[+~------------]+ | ok |
| +[+~[-----]-----]+ | ok |
- Simple loop support: yes
- Nested loop support: no
- Incomplete sensitivity list; missing signals: RESET, pcVal
- Possible problems with signals: DATA_RDWR, DATA_WDATA, OUT_DATA, instruction, pcValLoopStart