A hardware implementation of the Wordle word game, played with numbers instead of letters, built entirely in Verilog HDL and deployed on an Altera DE2 FPGA board with VGA output.
NumericalWordle is a 4-digit number guessing game. A secret number of 4 unique digits (0–9) is generated randomly on each new game. The player has 6 attempts to guess the correct number. After each guess, color-coded feedback is shown on a VGA monitor — green for correct digit in the correct position, yellow for correct digit in the wrong position, and grey for a digit not in the number. The sum of the 4 secret digits is displayed as a hint on both the VGA screen and the HEX displays.
| Component | Details |
|---|---|
| FPGA Board | Altera DE2 (Cyclone II EP2C35F672C6) |
| IDE | Quartus II 11.1 (32-bit) |
| Language | Verilog HDL |
| Display | VGA ×ばつ480 @ 60Hz |
| Button | Action |
|---|---|
| KEY0 (short press) | Cycle digit 0–9 |
| KEY0 (hold) | Confirm and lock digit into current slot |
| KEY1 | Move cursor to next slot |
| KEY2 | Submit current row as a guess |
| KEY3 | New game / return to start screen |
| Display | Shows |
|---|---|
| HEX0 | Currently selected digit |
| HEX4–HEX5 | Sum of the 4 secret digits |
| LEDR[5:0] | Remaining attempts |
| Color | Meaning |
|---|---|
| Green | Correct digit, correct position |
| Yellow | Correct digit, wrong position |
| Grey | Digit not in the secret number |
| White/Beige | Empty slot |
NumericalWordle/
├── top.v # Top-level module — wires everything together
├── input_handler.v # Button debounce, short/long press detection
├── digit_selector.v # Cycles current digit 0–9
├── guess_register.v # Stores current row guess, manages cursor and locks
├── game_memory.v # Stores all submitted guesses, tracks win/lose
├── comparator.v # Green/yellow/grey logic (two-pass algorithm)
├── secret_number.v # LFSR-based random number generator
├── tile_color.v # Outputs RGB color per tile based on state
├── digit_drawer.v # 7-segment style pixel font renderer
├── hex_decoder.v # 7-segment HEX display decoder
├── vga_controller.v # VGA sync signal generator (×ばつ480 @ 60Hz)
├── clock_divider.v # Divides 50MHz clock to 25MHz
├── NumericalWordle.qpf # Quartus project file
└── NumericalWordle.qsf # Quartus settings and pin assignments
The DE2 board provides a 50 MHz crystal oscillator. A clock divider halves this to 25 MHz for the VGA pixel clock. All game logic runs on the 25 MHz clock. On every rising edge, all registers update simultaneously — this is the fundamental difference between FPGA hardware and software.
A 16-bit Linear Feedback Shift Register (LFSR) runs continuously on every clock cycle. When the player presses KEY3 to start a new game, the LFSR is at an unpredictable state, producing effectively random output. A state machine then samples the LFSR to pick 4 unique digits (0–9), rejecting any digit already chosen.
The comparator runs in two passes to avoid double-counting. Pass 1 finds all exact matches (green) and marks those secret digits as used. Pass 2 scans remaining unmatched guess digits and checks if they appear anywhere else in the secret number (yellow). Anything remaining is grey.
The VGA controller generates hsync and vsync signals and exposes the current pixel coordinates (x, y). For each pixel, combinatorial logic decides what color to output — checking whether the pixel falls inside a tile, inside a digit segment, inside the title text, or inside a win/lose overlay box. There is no framebuffer; every pixel is computed on the fly.
The game has three states: Start Screen (shows controls and color legend), Transition (diagonal wipe animation), and Playing (the game grid). KEY3 moves between states.
- Open
NumericalWordle.qpfin Quartus II 11.1 - Compile the project (Processing → Start Compilation)
- Program the DE2 board via USB-Blaster (Tools → Programmer)
- Connect a VGA monitor to the board
- Press KEY3 to start the game