Exploring the world of RTL Design, FPGA Prototyping, and ASIC Flows. Proficient in SystemVerilog, Verilog, RISC-V Assembly, and C++, I love bringing silicon ideas to life with SystemVerilog, RISC-V, and FPGA tools.
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🔭 I’m currently working on RISC-V SoC Design, Verification & FPGA Prototyping
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🌱 Learning SystemVerilog | UVM | ASIC Physical Design
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👯 Open to collaborate on RISC-V & Custom EDA Projects
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💬 Ask me about RTL, FPGA, Verilog, SystemVerilog
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📫 Reach me at muddassiraliofficial@gmail.com