RV少年 (RV4Kids)

从 Netlist 到 GDS 的开源芯片设计 EDA 平台

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🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

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Open-source high-performance RISC-V processor

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This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.

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RISC-V SoC designed by students in UCAS. - Open Source Chip Project by University (OSCPU) Let students design their own chips!

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projects/soc目录下存放了接入ysyxSoC的示例程序。源码中只有一个占位符,能够通过编译但不能正常运行。 要使用该框架,需要先按照 ysyx SoC 的 readme 完成 命名规范 和 CPU 内部修改 两个步骤,得到 ysyx_21xxxx.v,

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