Talk:Reduced instruction set computer

The lead presently says:

Reduced instruction set computing, or RISC (pronounced 'risk', /ɹɪsk/), is a CPU design strategy based on the insight that a simplified instruction set provides higher performance when combined with a microprocessor architecture capable of executing those instructions using fewer microprocessor cycles per instruction. A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing (CISC).

There's a few problems here besides the issue raised at Talk:Reduced instruction set computer#Requested move 10 May 2017:

• To say that RISC is a CPU design strategy could be misunderstood by laypeople as self-contradictory given that a CPU is understood to be a part of a computer, yet the "C" in "RISC" means "computer". A person familiar with the topic would understand that whilst some sources describe RISC as such, its because of the inadequacies of the language in reconciling how the idea was originally framed and how it is framed today. RISC is better described as a type of computer.
• "Microprocessor architecture" implies that RISC is intrinsically linked to microprocessors. Whilst that's the popular narrative, it's wrong. The first RISC was the IBM 801, and it wasn't a microprocessor.
• "Microprocessor architecture" is linked to "microarchitecture"; "microarchitecture" is not a contraction of "microprocessor architecture".
• The use of cycles per instruction (CPI) to mean instruction latency is completely wrong. To speak very generally, CPI is an average of all measured instruction latencies.
• "Microprocessor cycles per instruction" is meaningless, there's no need to qualify "CPI" with "microprocessor".

I've improved the lead as best I can, but given the complexity of the topic, it's probably still be inadequate. 50504F (talk) 07:35, 26 May 2017 (UTC) [reply ]

50504F, Thank you, those improvements made the lead much better. I agree that RISC not just a "design strategy", but a more-or-less objective type of hardware that can be distinguished from other types of hardware no matter what "design strategy" was used to develop it.

I'd like to suggest 2 further improvements:

* Alas, the current lead claims RISC has something to do "with a small ... set of instructions," a common misunderstanding that is specifically called out in the reduced instruction set computer#Instruction set philosophy section and the reduced instruction set computer#Comparison to other architectures section.

* I feel that RISC is better described as a type of CPU, rather than a type of computer. In my view, the things that make RISC different than the alternatives (TTA, CISC, DSP, etc.) only affect the CPU and have little or no effect on the other parts of computer architecture -- main memory, I/O, caching, etc. -- or other parts of a physical computer -- the form factor, the power supply, whether it has a single-chip CPU (microprocessor) or a discrete-transistor CPU or something else, etc.

--DavidCary (talk) 22:06, 12 January 2021 (UTC) [reply ]

I think the lead is in reasonable shape now and I am removing the {{Technical }} tag. ~Kvng (talk) 16:12, 15 May 2023 (UTC) [reply ]

This seems like a grab-bag of different RISC architectures with arbitrary categories. Why are gaming systems considered low-end? — Preceding unsigned comment added by Indolering (talk • contribs) 03:38, 22 March 2021 (UTC) [reply ]

I guess the theory is to indicate where RISC is being used, for the benefit of people who think x86 rules the world, but it is, indeed, a not-well-organized grab-bag. It's not particularly up-to-date, with several of the examples no longer applying, and some items just mention instruction sets without giving current examples where it's used.

At this point, the currently relevant RISC architectures, as I see it, are:

• ARM, obviously, from microcontrollers to supercomputers;
• SPARC, which is still being sold in servers;
• Power ISA, which is still being sold in servers;
• perhaps others used in embedded applications. Guy Harris (talk) 06:15, 22 March 2021 (UTC) [reply ]

It is a common game to claim (computer X is the first risc) based on some simplified definition of "what is risc?". The book making the claim that ACE is RISC is visible on Google Books here (for me at least, YMMV).

The (relatively short) article in question defines risc in a somewhat hand-waving manner, saying "no one at the time would agree with this definition" which is (top of page 199) essentially of "microcode slows execution, and long pipelines are slow and have interlocks". That is a rough description I could find much to agree with.

Then he attempts to link the two with the arguments that in ACE, "ease of programming had knowingly been sacrificed to speed", followed by sections noting it lacked microprogramming, that it could be simplified using interpreters, and then concluding "We can indeed conclude that the ACE is a RISC machine in the sense of having an architecture heavily influenced by the design of the computer".

None of these statements are part of the definition he posts. This is not surprising, as none of the definitional ideas even existed and would take the better part of a decade to emerge. The fact that it didn't have them is akin to claiming that horse carriages are really ICE automobiles because engines didn't exist at the time and the designers were all interested in speed.

If I sound dismissive, I am. Regardless of Turing's original desires, ACE emerged as a pretty bog-standard drum machine. That is by no means a denigration - it's bog standard because everyone used the concepts he helped develop. But the claim that it is a proto-RISC fails by the author's own definition as no machines of the era had the very features he quotes as definitional.

I'm not averse to new claims for first, but I am rather averse to the sort of hand-waving, wooly-headed argument presented in this article and the claim demands much better support in order to deserve being included here. Maury Markowitz (talk) 14:30, 4 January 2022 (UTC) [reply ]

Unfortunately, I can't find back the source of this acronym, it was iirc a document of IBM that described the development of the powerpc out of the rs6000 and/or 360 series computer. I Think it's worth mentioning it in the article if the source can be found. The increased speed of RISC cpu's doesn't come from simplicity but from overlapping instruction cycles, an important difference. The overlapping architectures could only be fit in older fpga's by reducing the instruction set, which led to the modern (defacto) meaning. 84.80.95.139 (talk) 22:35, 10 October 2025 (UTC) [reply ]

This "Principles of Digital Design" slideshow used the term "Reduced instruction-set cycle" as the title of a slide that appears to be talking about RISC. Whether the instructor coined the term as an alternative expansion of "RISC" is unknown. It's talking about a load-store architecture:

* Register (add, shift,...) and misc. (set, clear,...) instructions do not need address fetch and effective address computation

* Memory (load, store,...) and control instructions (jump, branch,...) do not need operand fetch and operation execution

* Thus, we can share operand fetches and address fetches

* We can also share operand execution and effective address computation

* Therefore, instruction cycle is reduced to 4 steps

and a key, perhaps the key, component of RISC is a load-store architecture, in which arithmetic is register-register and loads and stores do no operand arithmetic, just address-calculation arithmetic.

The PowerPC instruction set was a modification of the IBM POWER instruction set architecture (all POWER and PowerPC processors were capable of executing the "common" instructions between the two; some executed the POWER-only instructions, some executed the the PowerPC-only instructions, and I think some executed all of them). It came form the IBM 801 project, which was IBM's internal RISC project, started before both the Stanford MIPS and Berkeley RISC projects, and carried on independently.

IBM System/360 was a CISC instruction set, although it was one of the early general-purpose register-oriented designs, and probably influenced the development of other such designs. It also had somewhat simple subroutine-call instructions, that just put the return value in a register; most if not all RISC processors do the same.

So it was probably a "development of RISC at IBM" paper.

The overlapping architectures could only be fit in older fpga's by reducing the instruction set Early commercial RISCs were custom designs, not FPGA-based designs, as far as I know. Even the research designs may have been custom, and IBM's original 801 wasn't even single-chip. Guy Harris (talk) 00:06, 11 October 2025 (UTC) [reply ]

IBM also used the phrase "reduced instruction-set cycle" in this Redbook about the PowerPC 970 processor. Guy Harris (talk) 00:10, 11 October 2025 (UTC) [reply ]