Talk:AArch64

I am not sure if the full v8a instruction set was implemented or just address space was extended to to 2TB(64bit)?

And need to add some product implementations ie. SSD/hdd models.
--:GSMC(Chief Mike) Kouklis U.S.NAVY Ret. ⛮🇺🇸 / 🇵🇭🌴 ^⍨talk 09:21, 10 May 2021 (UTC) Reply

Why would it implement the v8-A version of A64, rather than the v8-R version of A64, given that it's a Cortex-R core?

And, according to the Arm Architecture Reference Manual Supplement - Armv8, for Armv8-R AArch64 architecture profile, section B1.1:

The Armv8-R AArch64 application level programmers’ model differs from the Armv8-A AArch64 profile in the following ways:

• Armv8-R AArch64 supports only a single Security state, Secure.
• EL2 is mandatory.
• EL3 is not supported.
• Armv8-R AArch64 supports the A64 ISA instruction set with some modifications.

The main changes appear to be some memory-barrier instruction changes. Guy Harris (talk) 20:21, 10 May 2021 (UTC) Reply

What do "SSD" and "hdd" stand for? If they stand for "solid state drive" and "hard disk drive", presumably you're referring to disk drives using 64-bit Armv8-R processors as controllers. If that's the case, that might belong in pages about particular Arm cores used in those drives, rather than the AArch64 page. Guy Harris (talk) 20:24, 10 May 2021 (UTC) Reply

@Comp.arch: "conda-forge.org: "ARMv8 64-bit (formally known as `aarch64`)", just their terminology, or official?"

Presumably the intent was to ask that question here; edit comments unrelated to the edit are not the right way to ask questions about the article. Please ask them on the talk page, instead.

AArch64 is an official Arm term. As of 2022年01月10日, the current edition of Arm® Architecture Reference Manual Armv8, for A-profile architecture says:

This manual describes the Arm® architecture v8, Armv8. The architecture describes the operation of an Armv8-A Processing element (PE), and this Manual includes descriptions of:

* The two Execution states, AArch64 and AArch32.

* The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the Arm architecture.

— In AArch64 state, the A64 instruction set.

So:

We have the Arm Architecture, or the Arm CPU architecture.

It has multiple versions, including versions 7, 8, and 9.

Some of those versions have one or more profiles - the A-Profile, the R-Profile, and the M-Profile.

ARMv1 through ARMv5 have no profiles or execution states. According to the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, ARMv4 had only the ARM instruction set, ARMv4T added Thumb, ARMv5T was the first v5 and included Thumb, ARMv6 included Thumb, and ARMv6T2 added Thumb-2.

ARMv7 introduced the profiles; an ARMv6-M profile, with Thumb only, was introduced either at that time or afterwards, but they didn't split the existing ARMv6 into ARMv6-A and ARMv6-R, as far as I can tell. ARMv7 was still 32-bit-only, with no execution states. ARMv7-A and ARMv7-R have both ARM and Thumb (including Thumb-2). ARM-v7M is Thumb-only (including Thumb-2).

Armv8 also has the profiles. It calls the ARM instruction set A32, the Thumb/Thumb-2 instruction set T32, and the new 64-bit instruction set A64. [Armv8-A introduced the execution states; I'm not sure whether a 32-bit-only or 64-bit-only implementation is allowed. Armv8-R also has AArch32 and AArch64. ARMv8-M supports only T32.

I presume this whole mess is due to 1) trying to support everything from the microcontroller market to the server and supercomputer markets, 2) allowing that broad customer base a choice of options for their application, and 3) the instruction set now having this all designed in from Day One so it has to get added on.

AArch64 is probably what "ARMv8 64-bit" could be called, although it's not unique to ARMv8 any more, as per the Arm® Architecture Reference Manual Supplement Armv9, for Armv9-A architecture profile, Issue A.a. As far as I can tell, "ARMv8 64-bit" is not an official Arm term (if nothing else, if it were, it'd be "Armv8 64bit" :-)). Guy Harris (talk) 02:49, 11 January 2022 (UTC) Reply

And Arm's term for AArch64 and AArch32 is "Execution state" - a processor can be in AArch64 state, in which case it fetches and executes A64 instructions, or in AArch32 state, in which case it fetches and executes A32 or T32 instructions, depending on whether it's in "ARM" or "Thumb" mode (or whatever they call them now). The mode can change on an Exception level change, so trapping from a 32-bit application to a 64-bit OS kernel, or from a 32-bit OS to a 64-bit hypervisor, would switch from AArch32 to AArch64 on an EL0 -> EL1 or EL1 -> EL2 Exception level change, and returning from the latter to the former would switch from AArch64 to AArch32.

(I.e., it's not as if "AArch64" is an architecture with both 64-bit and 32-bit support. A processor with both 64-bit and 32-bit support can run in either AArch64 state or AArch32 state; a processor with only 64-bit support only supports AArch64 state and a processor with only 32-bit support only supports AArch32 state. I'm trying to find some documentation on whether either of those two are required by Armv8-A, or whether an Armv8-A processor is allowed to support only AArch64 or AArch32. Some hypothetical company that designs its own Armv8-A chips and develops its own operating systems could, if its Arm architecture license allows it, develop AArch64-only chips to run versions of its OSes that lack support for 32-bit applications, for example.) Guy Harris (talk) 09:02, 30 May 2024 (UTC) Reply

Research the following and if you find any details about the following, please include them with their sources:

1) ARMv9.6-M

2) ARMv9.6-R

78.190.164.190 (talk) 16:18, 4 December 2024 (UTC) Reply

...if they're involved with 64-bit ARM. This isn't an article about ARMv8 and later, it's an article about 64-bit ARM; 64-bit ARM was introduced in ARMv8-A, and later added to ARMv8-R, but ARMv8-A and ARMv8-R do not require support for 64-bit ARM; both 32-bit ARM and 64-bit ARM are optional in ARMv8-A and ARMv8-R, although you obviously need to support at least one of them.

ARMv8-M only supports the T32 instruction set (32-bit Thumb/Thumb-2), so nothing about the ARMv8-M belongs in this article. There are no signs of an M profile for the ARMv9 architecture at all on the Arm web site, and what stuff showed up elsewhere in a web search for "ARMv9-M" looked like pages that just assumed that ARMv9-M must exist, without bothering to do any research on it. See https://developer.arm.com/Architectures/M-Profile%20Architecture for the M profile.

ARMv8-R supports AArch32 (with A32 and T32) and AArch64 (with A64) but, as noted, doesn't require either. There is no evidence of any flavor of ARM9-R anywhere on the Arm developer site, just as there is no evidence of ARMv9-M. ARMv8-R AArch64 support is already discussed on this page.

There is no requirement that, if ARMv9.x-A exists, that either ARMv9.x-R or ARMv9.x-M exist. Guy Harris (talk) 09:03, 1 January 2025 (UTC) Reply

there doesn't appear to be any actual pages on what is exactly in a given extension. if i want to know what's in SVE2 i need to go through the entire page as an archaeologist, piecing together from incremental press releases. the official page "SVE" links as a redirect to the *middle* of this deluge of marketing material! Lkcl (talk) 19:39, 10 August 2025 (UTC) Reply

I've seen text that was generated by an LLM like ChatGPT and this is the proof from the source code.

=== Key Features of Armv8-R with AArch64 Support ===
# '''AArch64 Instruction Set (A64)''':
#* The A64 instruction<ref name=":0" /> set in the Cortex-R82 provides 64-bit data handling and operations, which improves performance for certain computational tasks and enhances overall system efficiency.<ref name=":2" />
#* '''Example Instruction''': <code>ADD X0, X1, X2</code> adds the values in 64-bit registers X1 and X2 and stores the result in X0. This 64-bit operation allows for larger and more complex calculations compared to the 32-bit operations of the previous A32 instruction set.
# '''Enhanced Memory Management''':
#* '''Memory Barrier Instructions''': The Cortex-R82 introduces improved memory barrier instructions to ensure proper ordering of memory operations, which is critical in real-time systems where the timing of memory operations must be strictly controlled.<ref>{title=Cortex-R82 Technical Reference Manual }</ref>
#** '''Data Synchronization Barrier (DSB)''': Ensures that all data accesses before the barrier are completed before continuing with subsequent operations.
#** '''Data Memory Barrier (DMB)''': Guarantees that all memory accesses before the barrier are completed before any memory accesses after the barrier can proceed.
#* '''Example''': In a real-time automotive control system, DSB might be used to ensure that sensor data is fully written to memory before the system proceeds with processing or decision-making, preventing data corruption or inconsistencies.
# '''Improved Address Space''':
#* '''64-bit Addressing''': AArch64 allows the Cortex-R82 to address a much larger memory space compared to its 32-bit predecessors, making it suitable for applications requiring extensive memory.
#* '''Example''': A complex industrial automation system can utilize the expanded address space to manage large data sets and buffers more efficiently, improving system performance and capability.
# '''Real-Time Performance Enhancements''':
#* '''Interrupt Handling''': With AArch64 support, the Cortex-R82 can handle interrupts with lower latency and improved predictability, crucial for real-time operations.
#* '''Example''': In a robotics application, the Cortex-R82's enhanced interrupt handling can ensure timely responses to external stimuli, such as changes in sensor data or control commands.

It's pretty much hard to fingerprint an LLM these days. I know that ChatGPT is trained on its own data and DeepSeek is trained on Chinese data and GPT-4o output. We need to stop LLM-generated and AI-paraphrased text on Wikipedia, like Stack Exchange did to make all content original. No human would write Wiki markup like that. That's an example of blindly copying and pasting text from ChatGPT writing Wiki markup. ZN2v8E (talk) 11:14, 22 September 2025 (UTC) Reply