Specify Xilinx FPGA DSP placement with Vivado

Question

How can I, either in the RTL or in a constraint file, map specific DSP blocks to certain locations? I see that DSPs are labeled by site, with names like DSP48_X5Y30 and I'd like to be able to map a particular DSP instantiation to that site.

I have a design a tiled design where, without constraints, Vivado places things reasonably within columns but arranges the columns in what seems like a random order, creating very long routing delays. It's basically a systolic array, so the data flow is simple; manually mapping an instantiation to the correct DSP site should be easy. However, when I trace Vivado's automatic placement, it's not uncommon for two columns that are logically adjacent to be on opposite ends of the chip, with the next column being back near where the first column is, requiring an entire round trip across the chip to traverse three stages.

When I look online, I see manuals on how to do this with ISE, but everything I've seen related to Vivado involves pblocks, which seems like an extra layer of indirection which is pointless for something this simple?

• user16324: Can you use UCF files with Vivado, or import them?
• FarhadA: Vivado does not support UCF any more

Answer 1

What you need to do is to create a location map for the block with the DSP blocks. Jusy for your info, Vivado does not support UCF file format any more.