STM32F4 pulse generator

Question

With STM32-H407 (STM32F407ZG), I am trying to make rectangular waveform output like;

---_ _ ---_ _ _ _ _ --- _ _ ---_ _ _ _ _ --- _ _ ---_ _ _ _ _ _

With numbers

---_ _ ---_ _ _ _ _ _ is 125us (0.000125s or 8kHz) long and it repeats.

--- is 3.5MHz or 0.2857 us long.
In other words, ---_ _ --- must be 0.2857 us + 0.2857 us + 0.2857 us long.

To summarize, 3.5MHz pulse pops twice every 8kHz.

What has been tried are 1) PWM + Timer. Failed to stop the 3.5MHz pulses after two cycles. 2) Timer + Timer. Timers did not work together.

How would you code this? Can you give some simple examples?

Thanks.

• JIm Dearden: Clarify the question. Mixing timing and frequencies like this makes this very difficult to read/understand what you are trying to do. You say the .2857uS pulse needs to 'pop' twice every 125uS but you seem to give an example where there are three pulses or is that ON-OFF-ON for equal 0.2857uS periods then OFF 124.1429uS?
• Roh: It's really simple. you can do it by counting the "tick"
• Joe Hass: Unless the CPU clock frequency is some multiple of 3.5MHz you have no hope of achieving the accuracy you have specified...down to tenths of a nanosecond. So what is the CPU clock frequency? How much jitter in the 125us can you tolerate...perhaps +/- 1us, with an average of 125us?
• nelm: @JImDearden Sorry for confusing. Forget about the first figure. .2857uS pulse needs to pop twice every 125uS. That is it. Thanks.
• nelm: @JoeHass CPU clock frequency is 168MHz but timer setting was 84MHz. 3.5MHz or a little less is fine. Jitter in the 125uS should be fine with +/- 10uS.

Answer 1

With the addition of a little bit of hardware you can reduce the demands on the controller. The main problem (pointed out by Dave) is that the frequencies are not multiples so it is difficult to synchronize them. The hardware syncs the rising edge of the 3.5Mhz pulses to the (asynchronous) output from the uC. The chips can be TTL (7400 series) or CMOS (4000 series)

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The uC produces the 125uS signal (interrupt timer). The 3.5MHz signal could be produced by an external Xtal oscillator and is simply a train of pulses at that frequency. It could also be derived from the uC oscillator through dividers.

The D type flip flop is positive edge triggered. When the output from uC is LOW the Q output of the flip flop is LOW. The AND gate output is also held LOW by the output pin of the uC (LOW). This means no pulses can get through the AND gate.

When the uC output pin goes HIGH the Q output of the flip flop has to wait until the next rising edge of the 3.5MHz clock before going high. Only when all three inputs to the AND gate are HIGH will the pulse be seen at the output of the gate. Because these signals are synchronized with the rising edge of the 3.5Mhz pulse the output will be a full length pulse.

The output from the AND gate is fed back to the uC which needs to detect TWO PULSES. On the falling edge of the second pulse it then resets the OUT pin to LOW which prevents any more pulses coming through the AND gate.

With the addition of a little more electronics the whole thing could be done totally in hardware.

Metacode

Initialise interrupt timer for 125uS

set output pin HIGH

check for first pulse going high --> low

check for second pulse going high --> low

Set output pin LOW

Answer 2

First, note that your overall period (125 µs) is not an integer multiple of your bit time (1/3.5 MHz). It's a factor of 375.5.

If I had to do this, I would be inclined to set up one of the SPI interfaces to run at 7.0 MHz and feed it a data stream via DMA that produced the pulses you need on the MOSI line. The data would be generated on the fly by the function that handles the DMA interrupts.

You can trade off the buffer size against how often the ISR needs to run. If you use double buffers, then you could tolerate quite a lot of jitter in the interrupt handling.