In SystemVerilog, can two always_ff blocks be executed in parallel?

Question

Some articles say that if I want to achieve different functions / tasks, it's better to separate the sensitivity list into multiple blocks. So, I'm wondering if I can really do this?

For example, instead of writing

always_ff @(posedge clk) begin
 b <= c;
 a <= b;
end

Can I write the following one to achieve the same function?

always_ff @(posedge clk) begin
 b <= c;
end
always_ff @(posedge clk) begin
 a <= b;
end

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I also found a similar question: In Verilog , if the always@ block is executed sequentially , how do non-blocking statements work since they are executed parallely?. But I don't know if it works for multiple always blocks.

Answer 1

Both codes result in the same two synchronous devices (non-blocking assignments). It is understandably confusing that the language used in the literature uses words similar to what we use in software. There is nothing being "executed" in parallel.

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If you use blocking assignments for the single "always block" with two assignments, b would be ignored by the synthesis tool and a single FF (or register) will be inferred.

Answer 2

Both of your options create the same hardware. Which you use is a matter of taste.

If your intention is to create a shift register, then the first form is easier to read, especially if you are reading it from a while ago, or someone else is.

If the two blocks just happen to communicate via the signal b, then it's perhaps clearer to separate them, especially as the blocks become bigger. But then, it would be better to choose a more descriptive name than 'b'.

At this low level of complexity there's no need to strongly prefer either one.