DDR with ARTIX 7 is not initialaizing

Question

We are using Artix7 200T in our design. We are using two independent DDR3L (MT41K512M16VRP-107 AAT) interface in our card. Both with 8Gb capacity with 16 bit data width.

Both DDR is completely independent except for 1.35V (both DDR is sharing same regulator). All address lines, Control lines and Data lines are not shared within memories. we have two board with us, in one board both DDR is working fine, but in second card, both DDR is not getting calibrated. the init_calib_complete satys as 0.

We have verified all the voltages including 1.35V, Vref and VTT. Also verified all the termination resistors. The DDR reset is also going high after programming. But the calibration still fails.

We have enabled the debug options in MIG IP, and we have seen that we are getting dbg_pi_phaselock_err=1 for both memories.

We have probed the dqs, but we are not getting any signal at DQS. Initially the DQS was at 1.35V level, after programming the level changed to 0.675.

We are getting continuous clock on DDR CK pins. For both Memories, the debug ILA results are same.

Please help us on how to debug this further. We are not sure whether the memory is faulty one as the chances are very less for both memory to fail together

• Chester Gillon: I haven't had to debug this myself, but does Debugging PHASER_IN PHASELOCKED Calibration Failures (dbg_pi_phaselock_err = 1) help?

Answer 1

The phaser in phase lock is one of the initial steps of DDR calibration. In this stage the controller will issue back to back read commands, so that the memory device will provide a continuous DQS, so that Phaser_in block will get a lock. As you have told below

We have verified all the voltages including 1.35V, Vref and VTT. Also verified all the termination resistors. The DDR reset is also going high after programming. But the calibration still fails. We are getting continuous clock on DDR CK pins

You have verified these, then there is chance that either FPGA or memory is a faulty one or assembly has some issues. You can check the address lines and control line while powering on check whether the FPGA is sending the read commands for the Phaser_in phase locking. . If FPGA is not sending these commands, chances are there the issue with FPGA or FPGA assembly. Verify all other interfaces are working in this FPGA, if possible try to configure the interface Pins as outputs and toggle the pins and verify it by probing. if all the lines are working fine, chances are less for issue in FPGA side

If the FPGA is sending these, then most probably the memory device is a faulty one or its not assembled properly. You can give a local reflow for the memories and test and if its not working still, try to replace one memory and check hope this helps.

• user398283: The FPGA was working fine, we have replaced the DDR and it is working fine