LPDDR4 layout, should we avoid having signals in same byte group on different layers?

Question

• Is it a bad idea to route intra byte DQx on different layers?

• I am trying to interface AM6442 to LPDDR4 16bit. I have followed every constraint in TI's DDR layout guidelines to the letter, maintining timing constraints, impeadence control, via symmetry, track spacing, etc. AM64x\AM243x DDR Board Design and Layout Guidelines

• The reference sources I found do not require that all the signals in the byte group are routed on the same layer, e.g. they don't forbid to route for example DQ0 and DQ1 on different layers

• However, I have not seen a single example of anyone spreading the byte group across layers. Everyone seems to route intra-byte signals on same layer. I understand routing them on same layer ensures one less parameter to worry about and avoid the need to simulate if everything is correct. But in my design, same layer routing seems to makes routing very tedious for length matching.

• Could someone explain the tradeoffs for keeping byte group on same layer vs. different layers. Is there something I need to consider or simulate differently if I use multiple layers?

• Has anyone tried a layout with the same data group signal on different layers and got it working? If so, what parameters did you control to get it working? OR If you failed to get it working, what do you think were the reasons for it?

• jsotola: your last question asks for an opinion ... such a question is not allowed here
• Bubu: @jsotola What ill-logical argument is this? I am clearly asking for observations/experimental results. How does that translate to asking for an opinion? It's almost impossible to have a little amount of opinion in questions and in answers. All everyone wants here is to share or gain knowledge; what is so wrong with that? Why is everyone here lately more interested in how the question was made than the actual question itself?
• jsotola: there is no wrong answer to that question
• BK303: @jsotola proposed some edits that I think clarifies the OP desire to understand the tradeoffs and differences in between routing options, which is reasonable question.
• Ryan: I understand routing them on same layer ensures one less parameter to worry about and avoid the need to simulate if everything is correct. I would recommend simulating it anyway. Extra money and effort up front often saves a lot of money and effort down the road. I've seen more than one DDR board fail their first time when they made a mistake that would have been caught with simulation.

Answer 1

I believe your question is why do many example DDR PCB layout designs route the all the signals in a byte group on the same layer?

The TI DDR routing app note you referenced is very nice and great that you read it carefully. As you know from reading section 2.16 Data Group Routing Specification, the byte group skew (difference in propagation time) requirement is very tight, but is just across DQSn+/-,DQMn, and DQx within the same byte group, with no requirement between or across byte groups.

I do have experience with DDR layouts, and I've also chosen to keep each byte group on same layer when possible because the delay match is more predictable with such a layout, even if as you say this choice "makes routing very tedious 'specially in length matching." Remember, physical trace length matching is an approximation for propagation time delay matching, and what really matters is the overall propagation time difference must be minimized so that the signals arrive together within a tight window of time. The following factors will make comparing trace length a less reliable predictor of relative propagation time:

• Different numbers of vias transitions end-to-end (unless skew analysis adds a via delay estimate)
• Different lengths or types of vias end-to-end (unless skew analysis adds specific via delays that are different for each possible layer transition or via type)
• length of trace on micro-strip vs strip line layers (unless skew analysis compensates for difference in propagation speed across surface vs. inner layers)
• differences in return layer transitions due to distances to ground vias or bypass caps (hard to compensate for without EM field based simulation)

So basically, if a byte group is kept on the same layer, then all traces will typically have identical counts and types of vias, and then the delays are more "what you see is what you get" with respect to using trace length matching instead of simulation. You pretty much answered your own question with your statement "I understand routing them on same layer ensures one less parameter to worry about and avoid the need to simulate if everything is correct."

Answer 2

Has anyone tried what I am asking and got away with it?

It really depends on the speed and what your margin is on trac's length.

I had a successful design with DDR4 at 1.6 GHz on a 8 layer PCB that worked fine. One thing you may want to consider is routing the clocks first then the address lines and then the data lines.

The data lines usually have much more margin on them and it doesn't matter as much.

The best thing to do would be to simulate it, but if you can't do that another thing is to estimate via delay in factor that into your length delay. I think my via's were something like 12 ps. But you also have to consider the fact that the via delay increases as you move down the layers, if you're going talk to bottom it'll be the full delay, but if you're going on the middle it'll be a fraction of that delay and this will also depend on capacitance. So I just tried to match them as best I could

Don't switch layers twice, route each pair on same layer and try and keep it on a similar layer to keep the via delay the same.

But really the best thing to do would just be to add a few more layers to your PCB it doesn't cost that much more and you would have working design. But if you really have to save 10 or 20 cents per square inch or whatever it is then I guess you have to work with what you have.

Could someone explain the tradeoffs for keeping byte group on same layer vs. different layers. Is there something I need to consider or simulate differently if I use multiple layers?

The goal is to make sure the signal arrives at the receiver before it is clocked. However you do that is up to the designer. Changing layers presents problems with capturing the differences between the layers. The Dk and Df can vary with different materials and thicknesses of transmission lines. Inner layers and outer layers can have differences. Via delays also can be tricky to capture. So the recommendation is to route signal groups on the same layer.

If you don't do this then you have to capture all this, put it in the simulator or do hand calcs. Much easier to keep it in the same layer. In higher speed designs, this may be a necessity if the margins are 10ps or lower.