FPGA Internal timing/ timing constraint

Question

When I connect several vhdl components to create one design, how do I ensure that the fpga's internal (ex. register to register) setup and hold timing is not violated?

Ex. Data bus between components is sampled correctly on rising clk edge.

• user3624: All FPGA tools have some way to set and verify timing constraints. Just use those tools.
• JakobJ: I probably missing something, but all the timing are related to clk vs. output/input pins.
• user3624: You are missing something. Look for clock frequency/period constraints.

Answer 1

When you create a constraint for your clocks, the synthesis and P&R tools of the FPGA use that as the guideline to route your design.

It is not only for the In/Out signals, but for every flip flop in your entire project.

If you have multiple clocks in your design and you have regions where signal cross different clock domains, you have to explicitly tell your P&R tool to either ignore those path (make them FALSE_PATH) or create a multi_cycle path between these 2 clock domains.