MachXO2 VHDL Internal Oscillator - "ERROR: formal nom_freq is not declared"

Question

I am trying to run the code below, but I get an error on line generic map(NOM_FREQ => "2.56"); and I am very confused why. The error says "ERROR - c:/desktop/latticeprojects/tut/top.vhd(53): formal nom_freq is not declared. VHDL-1084". I am using the Lattice Diamond software and a MachXO2 board, and this code is copied from their User Guide. When I comment out the generic map line, it compiles.

I also don't really understand the point of using the attributes here, and why wouldn't it throw an error if OSCInst0 is instantiated after the attribute NOM_FREQ of OSCInst0 : label is "2.56"; line?

Why am I getting an error about NON_FREQ not being declared? Why are there attributes being used here when generics have default values? Any advice on this issue, and why we need these attributes, would be greatly appreciated! Thanks.

I took this code pretty directly from their User Guide, so I am confused what the issue is.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library lattice;
use lattice.components.all;
library machxo2;
use machxo2.all;
entity top is
 port(
 OUT1 : out std_logic;
 TP2 : out std_logic
 );
end entity;
architecture behav of top is
--internal oscillator
component OSCH
 -- synthesis translate_off
 generic (
 NOM_FREQ: string := "2.56"
 );
 -- synthesis translate_on
 port (
 STDBY: in std_logic;
 OSC: out std_logic;
 SEDSTDBY: out std_logic
 );
end component;
attribute NOM_FREQ : string ;
attribute NOM_FREQ of OSCInst0 : label is "2.56";
signal stdby, osc_int, stdby_sed: std_logic;
begin
 
 OSCInst0: OSCH 
 generic map(NOM_FREQ => "2.56");
 port map(
 STDBY=> '0',
 OSC => osc_int,
 SEDSTDBY => stdby_sed
 );
 
end behav;

Answer 1

I'd originally answered this but it didn't fix the problem:

• In your instantiation, delete the semi-colon before port map.

---

Revised answer:

This appears to be part of a known problem with Lattice Diamond IDE, as far back as 2015. Looking in 'Lattice Software Known Issues (Feb 2015)', there's the following statement on p8:

enter image description here

They give the following fix:

If you see this problem, open the .vhm file with a text editor
and change the two lines to:
library pmi_work;
use work.pmi_components.all;

• jukebox41188: It originally didn't have the semi colon and I was still getting the error, I thought adding it might fix it. I just tried to compile again without the semi colon and got the same error. I also tried commenting out the generic map line altogether and it compiles fine, so I guess the generic map isn't necessary when there is a default value assigned?
• TonyM: @jukebox41188, like you're seeing, generics don't have to be mapped and default values will be used. (Different compilers/simulators may give a warning anyway if you do.) Dumping "generic map" obviously isn't giving you a solution or an answer to your question. My answer's correct as the map's ';' is not standard VHDL but I can't explain why you get an error without it. Are you sure that OSCH isn't a component in one of the libraries? Try renaming 'OSCH' to 'xx_OSCH' or something else unlikely.
• jukebox41188: I am using Lattice Diamond IDE, and I confirmed that the OSCH module does exist in their library, but it is in Verilog. The NOM_FREQ variable is a parameter in the Verilog file, so maybe there is a different way to reference that in VHDL? Also, I tried switching the name to 'xx_OSCH', and I am still seeing the same error. If the xx_OSCH module doesn't exist, why isn't it throwing an error for that? I am guessing this means it's not properly referencing the OSCH module either.
• TonyM: @jukebox41188, had you seen the revised answer and been able to try it out yet?
• jukebox41188: Thank you! That seemed to work.