What is the need for implementing synthesizable linked list module in RTL?

Question

Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.

Given that synthesized hardware has static memory size, what's the advantage of having linked list structure over array?

Answer 1

There are a lot of use cases. Some examples:

• incoming packets of different sizes need to be received and stored in a way that the OS can skip over one without reading its contents. Storing a length field is already a primitive form of a linked list
• for known flows, packet headers can be stripped off and stored separately, while the payload is appended to a payload buffer. A linked list is generated so the network stack can still inspect the entire packet as a whole if it needs to.
• outgoing packets can be assembled inside the network chip, pulling the headers from one area of RAM and the payload from another

• HWDesigner: Thanks for response. Can we not do these with arrays? Given that synthesized hardware has static memory size, what's the advantage of having linked list structure over array? Trying to wrap my head around the array vs linked list part.
• Simon Richter: Pretty much all of these are on the interface to a host PC, so we're using the host's memory here, not BRAM, and in larger quantities than we have BRAM available.

Answer 2

Regardless of whether you mean network (co-)processors (or hardware accelerators for computer networking) or network-on-chips (NoCs) by "network chips," the terms "linked list" and array are used interchangeably by many people without a computer science, or even computer engineering, background.

You want to store incoming packets for either case, network processors or NoCs, in the buffers that are realized as linked lists or arrays.

Silicon implementations of circuits and electronic systems cannot be dynamically expanded/reduced.

Hence, they effectively mean the same thing.