FPGA controlled ADC has undefined data

Question

I have an MAX11116AUT-T ADC Controlled by an FPGA at a 6.25MHz clock. Once the CS signal is set to low, I can see data being returned by the ADC on the falling edge of the clock.

There is, however, a very short spike visible sometimes, and only once the CS is low. The odd thing about this spike is that it disappears not by definition on a falling edge of the clock so I wonder how it is generated and whether this peak could indicate a valid bit but is missed by the FPGA. The FPGA only checks on the rising edge as would be normal according to the MAX11116AUT-T Datasheet. Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max11102-max11117.pdf

I have connected the output first to an oscilloscope to see what's happening, later I also connected a Logic Analyzer.

The oscilloscope's measurements:

• Dark blue: analog signal;
• Yellow: Clock;
• Aqua: Chip Select (active low);
• Purple: data Multiple measurements Zoomed in on spike

Logic Analyzer:

• Purple: clock
• blue: Chipselect
• Green: data

Logic analyzer's view

Specially from the Logic Analyzer's view it can be seen that a spike occurs but would never be registered by the FPGA since it falls to zero long before the rising edge of the clock occurs. Moreover, according to the device's datasheet this spike should not be there or last at least to the next falling edge.

Does anyone have a suggestion of what could cause such behavior? Please let me know when I should provide more information and if so, what information is desired.

For clarity, I did have the schematic that I use right here; (not much fancy I guess).

Schematics

• pm101: If you could share an extract of your schematic especially around the ADC . It appears that DOUT of the ADC is a three-state output - I suppose that has been taken into account?
• Mart: Thanks so much for helping, I appreciate that! I will add a schematic in a bit, but honestly I did not know and check that three state part. Neither do I actually understand what exactly it would mean. I see it now in the datasheet but would you mind explaining a bit about it? Also, I just saw that for normal mode, CS has to be pulled high after the 10th falling clock. Does it matter when exactly?
• pm101: It might be a red-herring but It just means that the pin has ability to go high impedance; I thought it might be an open drain output, it is not obvious from the datasheet but from looking at the example waveform in the datasheet it appears to only go three-state while CS is high or after 16th clock. Pulling CS high after 10 clocks is for fast data rate it appears, I'd try going slow first and make sure you're getting data.
• Mart: I did add a schematic. So, after reading your 2nd comment.. I'm not quite sure if there is something for me to try differently? Do you have a suggestion?
• pm101: Only thing I can think of is to beef up the power going to the MAX11116, Are you powering it from an FPGA out pin? Is there a more direct regulated source? You may also add a decoupling capacitor between MAX11116 VDD and GND. see pin description on datasheet Bypass VDD with a 10uF || 0.1uF capacitor to GND

Answer 1

I wouldn't worry about it. This is a very simple, low-latency SAR type ADC. The chip select controls the sampling, and the first data bit is output on the second clock cycle after that.

As far as I can determine, the output data appears to be essentially the direct output of the internal comparator fed through a transparent latch, so if the voltage on the sampling capacitor is drifting at all, there's some nonzero probability that the comparator output will change state while the clock is low. The datasheet only guarantees that the data is valid around the falling edge of the clock, which suggests that the latch is "holding" while the clock is high.