How to write tests for a clock signal

Question

I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests for a clock signal if it does make any sense at all.

-- hearbeat.vhdl
library ieee;
 use ieee.std_logic_1164.all;
entity HEARTBEAT is
 port (
 LEVEL : out std_logic
 );
end entity HEARTBEAT;
architecture RTL of HEARTBEAT is
 constant clk_period : time := 10 ns;
begin
 -- Clock process definition
 CLK_PROCESS : process is
 begin
 LEVEL <= '0';
 wait for clk_period / 2;
 LEVEL <= '1';
 wait for clk_period / 2;
 end process CLK_PROCESS;
end architecture RTL;

Edit: I come from a software background where is common that each component/unity/entity you create has an associated set of tests, doesn't mind how simple they are. I'm new to VHDL and I learned that each entity can be tested by creating a test bench. So my way of working until now was:

Create an entity called X_CHIP (pseudo-code):

-- x_chip.vhdl
library IEEE;
 use ieee.std_logic_1164.all;
entity X_CHIP is
 port (.. port definition ..);
end entity X_CHIP;
architecture RTL of X_CHIP is
begin
 .. architecture definition ..
end architecture RTL;

How I test X_CHIP (pseudo-code):

-- x_chip_tb.vhdl. Notice it is a different file
library IEEE;
 use ieee.std_logic_1164.all;
entity X_CHIP_TB is
end entity X_CHIP_TB; -- empty
architecture BEHAVIOR of X_CHIP_TB is -- not the architecture of X_CHIP but X_CHIP_TB
 component X_CHIP is
 port (.. port definition ..);
 end component;
 .. signal declarations ..
begin
 DUT_1 : entity work.X_CHIP(rtl)
 port map (.. port map definition ..);
 STIMULUS : process is
 begin
 assert .. report .. severity -- the tests themselves
 wait;
 end process STIMULUS;
end architecture BEHAVIOR;

That's why I thought the entity HEARTBEAT should have tests as well (a heartbeat_tb.vhdl file). But after reading some answers it seems that it makes no sense.

• Puffafish: You've written a test bench there, were's the code you're trying to test? Time doesn't really exist for synthesizable code, time only exists in test benches, and you use it to generate clocks to go into the modules under test. I'm not sure I understand your question, why would you need to test that a clock exists in the FPGA? Nothing would happen if there was no clock.
• chick3n0x07CC: @Puffafish I edited my question to add more context. I only have basic knowledge about FPGAs. Anyway, for now I don't pretend to use a real board (maybe in future) but play with waves in programs like GTKWave.

Answer 1

It makes sense to check a clock signal if it is generated inside your design. There are often different clock signals with different frequencies, different duty cycles and switch on and off functionality needed. Then you have to check all these features. The easiest way to do this is by creating a testbench where you insert only the clock generator module (and not your complete design). In this testbench you can have processes which are sensitive to a clock signal and measure and check the time between events by storing the VHDL variable "now" and comparing it to the value of "now" at previous events.

• chick3n0x07CC: Thank you, although an example would be very helpful. I also edited my question in case it adds more context.

Answer 2

Could check the clock frequency in a testbench by driving the output into a counter and checking the count at the end of a slower period.

• chick3n0x07CC: Thank you, although an example would be very helpful. I also edited my question in case it adds more context.