VHDL: Variables depending on other variables

Question

If I'm in a process and I have a variable (A) changing and a different variable (B) changing based on the original variable (A), does other variable (B) change based on the new value or the initial value of the first variable (A)?

For example:

example_proc : process (clock)
 variable A : unsigned (3 downto 0) := 0;
 variable B : unsigned (3 downto 0) := 0;
begin
 if rising_edge(clock) then
 A := A + 1; --First pulse is 0+1
 B := A + B; --Is first pulse 0+0 or 1+0?
 end if;
end process;

I know if those two variables were signals, then after then after the first pulse A would evaluate to 1 and B would evaluate to 0. I also know that if just A were a variable then A would evaluate to 1 and B would evaluate to 1 because the variable evaluates immediately. What happens if they're both variables?

Answer 1

What happens if they're both variables?

They both evaluate considering the value they just received.

if rising_edge(clock) then
 A := A + 1; --First pulse is 0+1
 B := A + B; --Is first pulse 0+0 or 1+0?
end if;

--Is first pulse 0+0 or 1+0?

1+0

If I try to evaluate B first will it be 0+0?

if rising_edge(clock) then
 B := A + B; -- First pulse is 0+0
 A := A + 1; -- First pulse is 0+1
 -- after first pulse: B = 0, A = 1
end if;

In other words, is ':=' blocking?

Blocking/non-blocking is a Verilog concept. Check this excellent answer for further information.