Basys 3 FPGA 7 segment display output delay

Question

I have an FPGA design for my Basys 3 that drives the board's 7 segment display to display some numbers. I'm using Vivado.

When I do the timing analysis, the constraint wizard asks me to set the output port delay (being this output ports the signals that go to the 7 segment display). How can I know what delays should I set?

• Meenie Leis: You don't have to constraint any delay to make it work, it's just an led circuitry with no setup n hold requirements.
• Martel: Can I tell Vivado to ignore those outputs when doing its processing?

Answer 1

There is no need to time those paths as there are no clocked synchronous elements with setup/hold requirement at the destination. You can either disable the timing of such paths using set_disable_timing constraint or simply use false_path constraint to exclude them from STA analysis, for e.g:

set_false_path -to [get_ports {o_data}]