Where are VHDL type cast functions defined?

Question

In VHDL one can cast one type to another using the name of the other type e.g

signal x : std_logic_vector(7 downto 0);
signal y : signed(7 downto 0);
...
y <= signed(x)

Here we use the type as if it was name of a function. Where exactly are these "cast functions" defined and why are they confused with the type name?

• user16145658: It's not a cast it's a type conversion , e.g. EEE Std 1076-2008 9.3.6 Type conversions "type_conversion ::= type_mark (expression ) ", an inherent basic operation (5. Types 5.1 General). There are rules (9.3.6) requiring types be closely related. Array types signed and std_logic_vector are closely related both having the same dimensionality and same element base type. Unrelated types would require conversion functions (e.g. to_signed found in IEEE package numeric_std).

Answer 1

"Signed" and "unsigned" are declared as "SUBTYPE" of "std_logic_vector", there is no need to declare cast functions.

It's a bit like in C when writing "(signed long)var"

• quantum231: I see, so this is the difference between cast and conversion function.
• user16145658: Prior to -2008 signed and unsigned are types. In -2008 and -2019 they are resolved subtypes of types unresolved_signed and unresolved_unsigned not std_logic_vector.