Does the "input" keyword do anything in a SystemVerilog function declaration?

Question

Is there a difference between these two SystemVerilog function declarations? Does the "input" keyword change any functionality? I've seen it both ways in examples.

function int addition (input int a, b);
 return a + b;
endfunction
function int addition (int a, b);
 return a + b;
endfunction

Answer 1

There is no difference between the two functions. In your code, the input keyword is optional. Refer to IEEE Std 1800-2017, section 13.4 Functions:

Function declarations default to the formal direction input if no direction has been specified. Once a direction is given, subsequent formals default to the same direction.