Efinity FPGA suite error EFX-0101

Question

When trying to synthesize an FPGA design in the Efinity FPGA Suite, I keep getting the following error that I can't figure out how to resolve:

[EFX-0000 INFO] ... No sequential optimization performed on Clock Network SYNTHESIZED_WIRE_70
[EFX-0000 INFO] ... Sequential Optimization deduced 1163 equivalent points.
[EFX-0000 INFO] ... Sequential Optimization end (Real time : 10s)
[EFX-0101 ERROR] RUSHC IOs mapping failed (illegal pre-synthesis of tri-state elements: i12489).
Tue March 15 22 14:39:44 - D:/Efinity/2021.2/bin/efx_map finished. Exit code = 8 Exit status : Normal
Running synthesis flow fail. See exit code and exit status.
Tue March 15 22 14:39:44 - Running synthesis flow done. Duration = 0m 27.153s

• user16324: The error message is pretty obvious : you are doing something not supported with tri-state elements. As it's related to IOs, look carefully at how you are using the IO pins, especially if there is anything unusual about some of them (switching between input and output, or wired-OR like I2C)

Answer 1

It looks like this error was caused by a potentially high-impedance node being fed to a memory block. Here's a simplified example to reproduce the error:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Error0101 is
 port (
 clk: in STD_LOGIC;
 sel1: in STD_LOGIC;
 sel2: in STD_LOGIC;
 val1: in STD_LOGIC_VECTOR(7 downto 0);
 val2: in STD_LOGIC_VECTOR(7 downto 0);
 led: out STD_LOGIC
 );
end Error0101;
architecture SYN of Error0101 is
 signal xVal: STD_LOGIC_VECTOR(val1'RANGE);
 -- Infer RAM
 type ram_type is array (255 downto 0) of STD_LOGIC_VECTOR(val1'RANGE);
 signal ram_block: ram_type;
 signal addr_a: UNSIGNED(7 downto 0) := (others => '0');
 signal rddata_a: STD_LOGIC_VECTOR(val1'RANGE);
begin
 xVal <= val1 when sel1 = '1' else (others => 'Z');
 xVal <= val2 when sel2 = '1' else (others => 'Z');
 
 process(clk)
 begin
 if rising_edge(clk) then
 led <= '0';
 if UNSIGNED(rddata_a) > 63 then
 led <= '1';
 end if;
 if sel1 = '1' or sel2 = '1' then
 addr_a <= addr_a + 1;
 end if;
 end if;
 end process;
 -- Infer RAM
 process(clk)
 begin
 if rising_edge(clk) then
 if sel1 = '1' or sel2 = '1' then
 ram_block(to_integer(addr_a)) <= xVal;
 end if;
 rddata_a <= ram_block(to_integer(addr_a));
 end if;
 end process;
end SYN;

In my actual code, once I changed the bus to explicit MUX instead of hoping that the sythesizer would infer one, the error went away.