VHDL IF statement inside process statement

Question

I am learning VHDL. I have doubt regarding execution of If Else inside process statement. My code is :

entity test is
port(
 clk : in std_logic;
 reset : in std_logic;
 enable : in std_logic;
 a :in std_logic_vector(15 downto 0);
 b :out std_logic_vector(15 downto 0)
 ); 
 end test;
 
 architecture test_behave of test is 
 signal temp1:std_logic_vector(15 downto 0);
 type states is (state1,state2);
 signal present_state:states;
 
 begin 
 process(clk,reset)
 begin
 if(reset='1') then
 
 temp1<=(others=>'0');
 present_state<=state1;
 
 elsif(rising_edge(clk)) then 
 case present_state is
 
 when state1=> 
 if(enable='1') then--- if fir_enable='1' then NLMS block is enabled 
 temp1<=a; 
 present_state<=state2;
 else
 present_state<=state1;
 end if;
 
 when state2=>
 
 b<=temp1;
 present_state<=state1;
 end case;
 end if;
 end process;
 end test_behave;

Then I have added a testbench for evaluating this module. In that testbench, reset is high for first clock cycle and enable is low. At that time, present state is state1. Then in the next clock cycle, reset is made low and enable is made high and input data is given to a. The present state became state2. However temp1 variable didn't get the value of a in the same clock cycle even though both temp1 and present state are both signals.

enter image description here

Answer 1

Temp is assigned on the first clock edge where all three of:

• Enable = true
• A has a value
• Present_state = state1

exactly as the code specifies.