How to accumulate samples coming into a memory block without using another buffer i.e sum with previous corresponding samples?

Question

So I have an 8k memory block in the FPGA. Samples come into it from outside the FPGA, from an ADC that has a source synchronous interface consisting of parallel transfers with a clock from the ADC. Each sample is 16 bits.

What I need to do is that whenever a new stream of samples starts to come in, I sum each new sample with its corresponding old value and write it back. Thus, rather than overwrite the old sample data, I would just sum the new values with corresponding old values. It is very important that the new sample be summed with a corresponding old sample and not some other sample. I cannot use two 8k RAMs I am afraid since memory is quite short.

Now all I know is that I need to start with a single 8k dual port RAM and use some form of pipelined operation while taking advantage of separate read and write ports on this dual port RAM. But, I am at total loss on how the design should be done. Is what I am trying to achieve even possible with a single dual port RAM with data coming into it ever clock cycle?

• Dave Tweed: Yes, it's quite possible. You just need to account for the pipeline delays created by the fact that inputs and outputs of the BRAM are typically registered. I'll write a more complete answer later.

Answer 1

The key is to realize that with the dual-port BRAM, the reading process on one port is really quite independent of the writing process on the other port. Despite the fact that they access the same physical memory, the write of any given address occurs several clock cycles later than the read of that address, so there's no data dependency created.

You just need to deal with the fact that BRAMs work best when both the inputs and the outputs are registered, which creates a relatively deep pipeline.

If we assume that your input logic can produce the address associated with each ADC sample at the same time as the data, then the pipeline looks something like this:

block diagram

• quantum231: Is there a special name for this peculiar design problem? I would expect it to have a name.
• user16324: Pipeline synchronisation. (I've even been known to get it right in a spreadsheet, before translating to VHDL, many years ago). One example here... stackoverflow.com/questions/14765205/…
• gyuunyuu: What program did you use to create this diagram by the way?
• Dave Tweed: @Quantum0xE7: It's called graphviz.