FPGA simulation with crystal oscillator what to do with XTL input?

Question

I instantiated a crystal oscillator (and CCC) in a Microchip/Microsemi IGLOO2 FPGA design, and the oscillator's VHDL module has a XTL input pin.

What is the proper preparation/wiring for simulation?

It is not clear to me from the documentation what to do with that pin:

"The crystal oscillator provides up to a 20 MHz clock signal. Physically, it requires connection to an external crystal, however, for simulation purposes the XTL pin provides a clock signal running at the desired input frequency."

It's an input pin, so how does it provide a clock signal?

To be clear, my question is not about crystal oscillators and how they work, it's about proper wiring in a testbench and in the top level.

Dec ref: https://coredocs.s3.amazonaws.com/Libero/11_8_sp4/sf2_mlg.pdf

• Tony Stewart EE since 1975: I would expect one pin is the input and its buffered output next to it used for feedback to the crystal.
• P2000: Maybe. But it's a macro so there are several connections not visible, and I think the crystal connection is transparent in the VHDL module, no feedback visible or anything (it's not an analog sim). I don't even understand why a XTL pin is needed for simulation: the osc module can just create the ref clock, which goes straight to the PLL, and is never used in the design anyway. We could then feed the test bench from the PLL... unless I am completely missing something here.
• Mitu Raj: I think you should attach the documentation for this particular IP.
• P2000: @MituRaj ok, done. I'd appreciate if you provided any of your insights, even if not device specific. I have a suspicion that the TB has to provide the XTL clock signal and it just gets passed through to the CCC/PLL, and as the FPGA top level the port is just left open. But I dislike guessing... and open ports.
• Mitu Raj: What I have understood is (if XTL is input of the macro), XTL is used only for simulation purpose when CCC is in XTLOSC mode. It emulates the crystal frequency that user uses on the board, and whatever clock frequency you feed there, you will get the same at CLKOUT in the simulation. For RC oscillator mode, it's irrelevant as the frequency is fixed on board and hence on simulation too.

Answer 1

My understanding of the description is that for simulation you feed XTL with a signal from your testbench corresponding to the frequency of your crystal to allow simulating different frequencies. Then continue to use CLKOUT in your design as if you had a real crystal.

For synthesis, either XTL is fed out of the top level and assigned to the correct pin, or it is left unconnected whereby the synthesis tools automatically map it to the correct oscillator hardware. Can't tell which.

• P2000: Yes this is the conclusion I am arriving at too. I'll give it a try and carefully read the log files (I still don't like unconnected inputs...).
• P2000: Confirmed: during simulation the XTL input must be fed a matching clock signal through the top level from the testbench, and for synthesis it is tied by the tool to the corresponding IO for the crystal, per the IO report.