STM32 Digital Inputs allowed voltage range

Question

I have an application where my STM32F0 is operating at 3.3V, I have some pins connected to a module which tries to talk to the STM32 first at 1.8V, then at 3.3V. I have configured all of the pins bar 1 as digital inputs, when I see that the pin I have configured as an analog input shows me that the bus voltage is 3.3V, I know I can now communicate with the module.

I have a colleague who is convinced that it is a bad idea to have 1.8V on the digital inputs, but I am not trying to read digital levels until the voltage on the interface is high enough.

Do you see any problems with having 1.8V on a digital 3.3V input? My colleague is convinced that the digital inputs can sync large current when the input is at this level, what is your opinion? I see no problem with the current setup

• rdtsc: Can this "1.8v first then 3.3v" behavior be changed in the module? If so, go that route.

Answer 1

This note is present in many STM32 datasheets (from stm32f030rc below):

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Despite the fact that is not a current in/out of the GPIO pin itself and that information on precise current and voltage values is not available in the notes, it may be a problem.

• Eoin O Connell: Thanks for the answer, do you think if a low impedance source is driving the signal at 1.8 that it can really sync a large current? Are we taking uA or mA?
• devnull: Your are welcome. I'd prefer not to speculate on figures that are not available for me but one good thing that I consider more clear from the note above is that the manufacturer is not talking about harmful currents for the component. The tone of the recommendations is much more in the direction of "if this is of concern for your application, you could do this or that".
• devnull: "if a low impedance source is driving the signal" I forgot to comment on that. You have not mentioned the specific uC but if you have not enabled the internal pull-up or pull-down resistors the input currents at DC are only due to leakage if the pin voltage is within the rails. The warning I quoted from the datasheet is talking about current between the rails, not at the GPIO pins.

Answer 2

Yes, it is possible that applying voltages around 1.8 V will cause high currents in the input circuitry of the IO pins. The switching threshold for CMOS gates is typically set near one-half of the supply voltage, or 1.65 V in your case. If the input voltage is close to that switching threshold then both the PMOS and NMOS transistors will be enabled, allowing large currents to flow directly from the power supply to ground.

Note that this can still happen if the IO pin is configured as an output, because the input circuitry remains electrically connected to the pin.

Will this cause a problem in your particular case? We don't have enough information to say one way or the other.

• Eoin O Connell: Thanks for the answer, do you think if a low impedance source is driving the signal at 1.8 that it can really sync a large current? Are we taking uA or mA?
• Elliot Alderson: The IO inputs are usually very high impedance anyway, so a low impedance source will not make any difference. Again, we don't have enough information to reasonably predict the magnitude of the current, but I would not be surprised to see several mA per pin.