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I'm using the S32K142 64-pin microcontroller.

I have a question about this table:

enter image description here

What parameter does the maximum sink current and source current depend upon?

The marked line in the table says that if the current sourced by the pin is 3.5mA, then the voltage on the pin is 3.3V-0.8V = 2.5V with respect to ground for a 3.3V supply voltage.

If that's the case, on what parameter does the minimum and maximum sourcing and sinking current of a GPIO depend?

JRE
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asked May 8, 2021 at 12:57
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3 Answers 3

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on what parameter does the minimum and maximum sourcing and sinking current of a GPIO depend upon

It depends on the output resistance of the GPIO pin, which is not informed directly and may not be symmetrical.

If you try to source more than 3.5 mA, the output voltage will drop below \$(V_{dd} - 0.8)\$ V.

If you try to sink more than 3 mA, the output voltage will rise above 0.8 V.

Both values are given for \$V_{dd} = 3.3\$ V.

Edit: regarding the question asked in the comments

It may vary even in the same uC (source AT89C51AC3 datasheet):

enter image description here

enter image description here

Others may focus more on all the internal interfaces (source ATmega328P datasheet):

enter image description here

Maybe the reason the manufacturers normally don't bother to show that in the documentation is that we don't need this information to use their devices.

answered May 8, 2021 at 13:04
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    \$\begingroup\$ Thank you for the answer. So, I understand it like, there's a CMOS configuration at each output pin. If we source more than 3.5mA, the output voltage will drop below 2.5V. So, the output impedance is 2.5V/3.5mA = 714ohms? And if we sink 3mA, the output voltage would be 0.8V approx. So, in this case, the output impedance (or say input impedance in the case of sink current), is 266ohms? \$\endgroup\$ Commented May 8, 2021 at 13:17
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    \$\begingroup\$ Yes, but note that only the worst case is given and the resistances only model what is likely a CMOS configuration as you mentioned. \$\endgroup\$ Commented May 8, 2021 at 13:19
  • \$\begingroup\$ Thank you. But Like, how can we figure out whether the internal outputs are CMOS? It is nowhere mentioned in the datasheet \$\endgroup\$ Commented May 8, 2021 at 13:30
  • \$\begingroup\$ I've also searched for that. Unfortunately I also could not find it in the document you linked and also not in the reference manual. \$\endgroup\$ Commented May 8, 2021 at 13:33
  • \$\begingroup\$ Yes, exactly. In that case, do you know what are the other types of Outputs apart from the CMOS outputs? So that I can google and read it \$\endgroup\$ Commented May 8, 2021 at 13:34
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We’ve been over this. The GPIO source and sink capability depends on the ‘on’ resistance of the P and N driver FETs, respectively, a topic I and others have already addressed in your previous questions. That parameter, Rds(on), isn’t in the datasheet, but can be derived from V(oh) and V(ol) at a given source or sink current.

Another name for this parameter is called drive strength.

Drive strength depends on two things:

  • Process characteristics
  • FET physical size

Drive strength is ultimately a statement of guaranteed Rds(on) that will satisfy the stated V(oh) and V(ol) at a specified source or sink current.

Why do they state it that way, as V(oh) and V(ol) rather than Rds(on)?

When the IC is manufactured, they test drive strength by putting a known source or sink current load on the pin and measuring the resulting V(oh) and V(ol), only accepting parts that are ‘strong’ enough to meet the datasheet spec, plus some margin. In other words, they use a functional spec that meets the system requirements to make valid high or low outputs.

Nevertheless, think of it this way, like a chip designer would: a FET is a resistor, which is in one of two states: infinite resistance when off, or at Rds(on) when on. It’s not more complicated than that. The fact that FETs behave like switchable resistors is one of their benefits over bipolar: it allows connecting them in parallel to reduce the overall Rds(on).

And some microcontrollers do exactly that, and further, allow selectively enabling parallel FETs to alter drive strength. This is helpful to reduce power dissipation and switching noise, or to match drive impedance to the system.

answered May 8, 2021 at 22:18
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The parameter would be the gpio mosfet on resistances. But the manufacturer doesn’t tell you that. What they do tell you is the minimum you can expect over temp and vcc. You can infer the on resistance via Ohm’s law then extrapolate what voltage you can expect at your given current.

As well, there may be thermal, bond wire and total current constraints.

answered May 8, 2021 at 13:16
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  • \$\begingroup\$ Thank you for the answer. So, basically, it is recommended to not increase source current or sink current more than 3mA? \$\endgroup\$ Commented May 8, 2021 at 13:19
  • \$\begingroup\$ 3.5 mA for source and 3.0 mA for sink - Yes. \$\endgroup\$ Commented May 8, 2021 at 13:30
  • \$\begingroup\$ Thank you for the clarification \$\endgroup\$ Commented May 8, 2021 at 13:31
  • \$\begingroup\$ ‘It depends’. Say I wired an led and resistor that drew 20mA. The actual port pin voltage drop might be over 1/2 vcc. Possible negatives are thermal - ie the chip gets too hot or gets a hot spot where the gpio driver is that accelerates electromigration and causes early failure of the chip or simply if you read the gpio state, the logic level is not quite what you think it is due to the voltage drop. Generally speaking, if the spec says 3.5mA sink, then you wouldn’t want to violate that for too long. Drawing 40mA current for a microsecond probably wouldn’t be an issue. \$\endgroup\$ Commented May 8, 2021 at 13:33

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