VHDL Counter Design Question

Question

How to design a counter to increment on the clock rising edge?

For example, I am trying to create a counter that increments on the rising edge of the clock if an input is a logic level 1. If the input is 0 on the clock rising edge, the counter is not incremented. When I write this logic, the code doesn't synthesise.

It seems like a counter enable signal I need after the clock edge detection but it won't synthesise.

EDIT

The error I am getting is:

[Synth 8-27] else clause after check for clock not supported 
[Synth 8-285] failed synthesizing module 'Encoder_Counter'

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Data_Sizes_Package.ALL;
entity Encoder_Counter is
 Port (Clock : in std_logic;
 Count_Input_A, Count_Input_B : in std_logic; 
 Reset_Counter : in std_logic;
 Counter_Value : out std_logic_vector(Data_width-1 downto 0)
 );
end Encoder_Counter;
 architecture Behavioral of Encoder_Counter is
signal Counter_Value_Temp : std_logic_vector(Data_width-1 downto 0) := (others => '0');
begin
Counter_Value <= Counter_Value_Temp;
 Process (Count_Input_A, Count_Input_B, Reset_Counter)
 
 begin
 
 if(rising_edge(Reset_Counter)) then --rising or falling edge?????
 Counter_Value_Temp <= (others => '0'); 
 
 elsif(falling_edge(Clock)) then
 
 if(Count_Input_A = '1' or Count_Input_B = '1') then
 Counter_Value_Temp <= Counter_Value_Temp + 1; 
 
 end if;
 
 end if;
 end Process;
end Behavioral;

• jwh20: Please post your code and any error messages you are getting when you try to synthesize it.

Answer 1

For anyone interested in this post in the future, the VHDL code in the question is very poor. This answer provides a better VHDL approach.

To summarise, the code should infer a counter with active high synchronous reset, that increments on the rising edge if either of the two inputs are high (OR gate logic).

The unsigned package is removed as it should not be used in VHDL - use numeric_std instead.

To properly code a synchronous design (register), the sensitivity list only requires the clock to be included (for active high synchronous reset as in this case).

The counter is now properly interpreted as unsigned and works as expected.

Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.Data_Sizes_Package.ALL;
entity Encoder_Counter is
 Port (Clock : in std_logic;
 Count_Input_A, Count_Input_B : in std_logic; 
 Reset_Counter : in std_logic;
 Counter_Value : out std_logic_vector(Data_width-1 downto 0)
 );
end Encoder_Counter;
 architecture Behavioral of Encoder_Counter is
signal Counter_Value_Temp : std_logic_vector(Data_width-1 downto 0) := (others => '0');
begin
Process (Clock)
 
begin
 
if (rising_edge(Clock)) then 
 if (Reset_Counter = '1') then
 Counter_Value_Temp <= (others => '0'); 
 
 elsif (Count_Input_A = '1' or Count_Input_B = '1') then
 Counter_Value_Temp <= std_logic_vector(unsigned(Counter_Value_Temp) + 1); 
 
 end if;
 
end if;
end Process;
 
Counter_Value <= Counter_Value_Temp;
end Behavioral;

• Mitu Raj: You can put the corrected code in the answer.
• David777: @MituRaj Will do when I get home.
• the busybee: You never did, would you mind to fulfill your promise?
• David777: @thebusybee This is very bad VHDL code and while I may have got the design to synthesize back in 2021, there are still many code flaws present which were never fixed (project ended).
• the busybee: Thank you, it makes the world some bits better (pun intended). Merry Xmas!