Storing Program Instructions on FPGA

Question

I am creating a basic RISC processing core on a FPGA development board (Nexys A7-100t).

I created a RAM block that will be used to store the instructions that my basic processor will execute to run a simple program. I have attached the file code for my RAM block below. Note it is not complete or been tested / compiled so there will be errors but it is just there to give you an idea of the RAM blocks functionality.

This code in theory generates the logic for accessing / sorting data but it doesn't initialize the RAM memory contents to hold the binary instructions.

My question is how could I initialize the RAM block upon power up or FPGA configuration?

My initial thoughts tells me I have the following options:

1. Generate the data 'manually' with VHDL code and LUT to write the data bytes to the RAM block. This might be the easiest option as there may only be approx 100 memory locations which are 32 bits wide.

2. Maybe Xilinx provides functionality to achieve this. I am not sure.

3. Use an SD card with the on-board SD card reader on the development board. Again unsure if this is viable.

4. Use an EEPROM to store the instructions and upon power up, write this data to the RAM block. I imagine this is no different than method 1. except for the hassle of reading the EEPROM contents serially while still having to load the data 'manually'. I do like the sound of using an EEPROM though.

I am interested to hear how everyone would do this. This is an academic project so doesn't require high speed, just low complexity and something repeatable.

Thanks for any help everyone!

RAM block VHDL file

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--add other required library files that holds 'Data_width' constant
entity RAM_Block
 Port ( RAM_Address : in std_logic_vector (Data_width-1 downto 0)); 
 Data_in : in std_logic_vector (Data_width-1 downto 0));
 Clock : in std_logic;
 Enable : in std_logic;
 Data_out : out std_logic_vector (Data_width-1 downto 0));
end RAM_Block;
architecture Behavioral of RAM_Block is
type memory is array (0 to 100) of std_logic_vector (Data_width-1 downto 0);
signal RAM : memory;
variable RAM_Address_int integer := 0;
signal RAM_output : std_logic_vector (Data_width-1 downto 0);
component Enabler_Block is
 Port ( D : in std_logic_vector(Data_width-1 downto 0);
 Enable : in std_logic;
 Q : in std_logic_vector(Data_width-1 downto 0));
end component;
begin
Enabler_Block_instance port map (D => RAM_output , Enable => Enable , Q => Data_out);
RAM_Address_int <= conv_integer(unsigned(RAM_Address)); 
 Process (Clock , Enable)
 begin
 if(rising_edge(Clock) and Clock = '1') then
 RAM(RAM_Address_int) <= Data_in;
 end if;
 if(rising_edge(Enable) and Enable = '1') then
 RAM_output <= RAM(RAM_Address_int);
 end if;
 end Process;
end Behavioral;

Answer 1

It is possible to initialize RAM blocks during configuration. In your code, you just need to set the initial values :

signal RAM : memory := (data,data,data,data...);

It is also possible from Vivado to declare which blocks are used for the program and then attach some file which be transferred into these blocks.

If you want to be able to load the program from an SD card or anything else, you could store in these RAM blocks a small loader program that will manage the transfers.

• David777: Ah right ok, so I think the best method for my application is to manually initialize the RAM data in my VHDL code. And in your example above what do you mean "declare blocks that are used for the program and then attach some file which be transferred into these blocks"
• user16324: Write a Python script to create that VHDL code (perhaps a constant array in a VHDL package) automatically from whatever your data source is. Then signal ram : memory := mypack.myconst;
• David777: @BrianDrummond My python experience is limited. Sorry for my lack of knowledge, but what advantage does this offer over just typing in the VHDL code to initialize the data in the RAM?
• user16324: ... or other favourite language. (I've actually used VHDL for the purpose of generating VHDL too!) Advantage depends on your data source, and maintenance. If it's a CSV file from a spreadsheet, or an object file from a compiler, or text from a book, or ... then about the third time you translate a set of changes by hand into VHDL source, the script will come out ahead.
• Grabul: Here is an example python script that generates VHDL constants from binary files : github.com/Grabulosaure/Intv_MiSTer/blob/master/src/intv/…