VHDL: Constraining Record with another record

Question

Let's assume I have a type of record containing unconstrained elements:

 type Axi4s_M2S is record
 Tvalid : std_logic;
 Tdata : std_logic_vector;
 Tstrb : std_logic_vector;
 Tkeep : std_logic_vector;
 Tlast : std_logic;
 Tid : std_logic_vector;
 Tdest : std_logic_vector;
 Tuser : std_logic_vector;
 end record Axi4s_M2S;

Now I implement two signals. "A" is completely constrained. The other one should be constrained using the first one.

signal A: Axi4s_M2S(Tdata(7 downto 0)......);
signal B: Axi4s_M2S(--constrain me likewise A);

Is there a way to do so?

• user16324: I'd look at subtypes of your base type which add constraints, and make A and B the same subtype.
• user8352: Note you type marks in the signal subtype indications don't match the type declaration. Otherwise use the subtype of A (noting record constraints were introduced in -2008 along with the predefined subtype attribute). signal B: A'subtype; (It'd have been easier to validate with a minimal, complete and verifiable example).(@BrianDrummond - the latest ghdl builds support this.)

Answer 1

With code that analyzes:

library ieee;
use ieee.std_logic_1164.all;
entity rec_constraint is
end entity;
architecture foo of rec_constraint is
 type Axi4s_M2S is record
 Tvalid : std_logic;
 Tdata : std_logic_vector;
 Tstrb : std_logic_vector;
 Tkeep : std_logic_vector;
 Tlast : std_logic;
 Tid : std_logic_vector;
 Tdest : std_logic_vector;
 Tuser : std_logic_vector;
 end record Axi4s_M2S;
 
 signal A: Axi4s_M2S(Tdata(7 downto 0), Tstrb(3 downto 0), Tkeep(3 downto 0),
 Tid(31 downto 0), Tdest(7 downto 0), Tuser(3 downto 0));
 signal B: A'subtype;
begin
end architecture;

VHDL -2008 supports record constraints in object declarations as well as a predefined attribute that returns the subtype of an object. With those the subtype of A can be used in the declaration of B.

Note that the record type declaration didn't match the type of signals A and B in the question nor was the record constraint complete.