Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ODT feature, however Address, Command, Control and Clock do not have the same ODT selection. None of these lines have termination resistors either. It is a working reference design, however I am unsure as to how and why the lack of termination is permissible in this case. Differential clock doesn't even have parallel termination.
I was not able to find any online source to indicate whether it is ok to leave point to point design unterminated (not counting ODT which is available for data/strobe/mask). If anyone could please refer me to a link/document I would greatly appreciate your help.
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\$\begingroup\$ Verify what I'm saying but someone asked a similar question on here a while back and I someone mentioned that DDR3 has terminations onboard. \$\endgroup\$DKNguyen– DKNguyen2020年07月13日 19:45:32 +00:00Commented Jul 13, 2020 at 19:45
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\$\begingroup\$ Yes, my DRAM has on die termination (ODT) for data, mask and strobe. It seems address, command, control and clock don't have ODT. \$\endgroup\$pcbguy– pcbguy2020年07月13日 19:53:37 +00:00Commented Jul 13, 2020 at 19:53
1 Answer 1
For a single DDR device with just one connection to address/command, using VTT termination is optional. Not using VTT termination can have lower performance as the signal margins will be reduced. Nevertheless it's very common on small systems with just one rank down on board.
This kind of connection relies on the host driver internal series resistance to absorb reflections from the far end. The signal looks quite horrible at the driver pin, but will be ok at the receiver.