Is SystemVerilog string manipulation synthesisable?

Question

I learnt that SystemVerilog provides a string datatype, which allows for many string operations, such as comparison, concatenation, length, etc.

Are those string operations synthesisable?

Answer 1

As I understand it, hardly anything in SystemVerilog is synthesisable; it's intended for use in testbenches and simulations.

• apalopohapa: This is not exactly true: "As of 2009, the SystemVerilog and Verilog language standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009)." (en.wikipedia.org/wiki/Verilog). So SystemVerilog is meant to be the new verilog, but with substantive extensions in verification.