VHDL: Getting U's for values after behavioral simulation

Question

Now, bear with me I am not very familiar with VHDL and I am only a beginner.

Why do the values of outputs remain uninitialized?

-- DESIGN4.vhd
 
--------------------------------------------------------------------------
--------------------------------------------------------------------------
--------------------------------------------------------------------------
library IEEE,WORK;
 use IEEE.STD_LOGIC_1164.ALL;
 use WORK.ALL;
entity DESIGN4 is
--vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv--
 port( A,B,C,D: in std_logic;
 F,G,H,I,J,K,L,M: out std_logic);
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^--
end; 
 
architecture STRUCTURAL_ARCH of DESIGN4 is
 -- component declarative region
 component AND_4 
 port( A,B,C,D : in std_logic ;
 Z : out std_logic);
 end component;
 
 component OR_4 
 port(A,B,C,D: in std_logic;
 Z : out std_logic);
 end component;
 
 component OR_3 
 port(A,B,C : in std_logic;
 Z : out std_logic); 
 end component;
 
 component OR_2 
 port(A,B : in std_logic ;
 Z : out std_logic);
 end component;
 
 component AND_2 
 port(A,B : in std_logic;
 Z : out std_logic); 
 end component;
 
 component AND_3 
 port(A,B,C : in std_logic;
 Z : out std_logic);
 end component; 
 
 component INV_1 
 port(A : in std_logic;
 Z : out std_logic); 
 end component; 
 -- signal declarative region
 signal A0,B0,C0,D0,H1,H2,I1,I2,I3,J1,J2,J3,J4,J5,J6,K1,K2,K3,K4,K5,K6,L1,L2,L3,L4,L5,L6,M1,M2,M3,M4: std_logic;
begin
 
 -- component instance and wiring region 
 -- Inverted inputs 
 Y1 : INV_1 port map (A => A, Z => A0);
 Y2 : INV_1 port map (A => B, Z => B0);
 Y3 : INV_1 port map (A => C, Z => C0);
 Y4 : INV_1 port map (A => D, Z => D0);
 -- instances and wiring for circuit F
 -- F = ABCD 
 CKT_F_G1 : AND_4 port map (A => A, B => B, C => C , D => D, Z => F);
 
 -- instances and wiring for circuit G
 -- G = A + B + C + D
 CKT_G_G1: OR_4 port map (A => A, B => B, C => C, D => D, Z => G);
 -- instances and wiring for circuit H
 -- H = A + CD + B'C' 
 CKT_H_G1 : AND_2 port map (A => C, B => D, Z => H1); 
 CKT_H_G2 : AND_2 port map (A => B0, B => C0, Z => H2);
 CKT_H_G3 : OR_3 port map (A => A, B => H1, C => H2, Z => H); 
 
 -- instances and wiring for circuit I
 -- AC'D'+BC+BD
 CKT_I_G1 : AND_3 port map (A => A, B => C0, C => D0, Z => I1);
 CKT_I_G2 : AND_2 port map (A => B, B => C, Z => I2);
 CKT_I_G3 : AND_2 port map (A => B, B => D, Z => I3);
 CKT_I_G4 : OR_3 port map (A => I1, B => I2, C => I3, Z => I);
 
 -- instances and wiring for circuit J
 -- J = A'C'D' + AC'D + A'CD + ACD'
 CKT_J_G1 : AND_3 port map (A => A0, B => C0, C => D0, Z => J1);
 CKT_J_G2 : AND_3 port map (A => A, B => C0, C => D, Z => J2);
 CKT_J_G3 : AND_3 port map (A => A0, B => C, C => D, Z => J3);
 CKT_J_G4 : AND_3 port map (A => A, B => C, C => D0);
 CKT_J_G5 : OR_2 port map (A => J1, B => J2, Z => J5);
 CKT_J_G6: OR_2 port map (A => J3, B => J4, Z => J6);
 CKT_J_G7 : OR_2 port map (A => J5, B => J6, Z => J); 
 
 -- instances and wiring for circuit K
 -- K = AC' + A'C + BD'+B'D
 CKT_K_G1 : AND_2 port map (A => A, B => C0, Z => K1);
 CKT_K_G2 : AND_2 port map (A => A0, B => C, Z => K2);
 CKT_K_G3 : AND_2 port map (A => B, B => D0, Z => K3);
 CKT_K_G4 : AND_2 port map (A => B0, B => D, Z => K4);
 CKT_K_G5 : OR_2 port map (A => K1, B => K2, Z => K5);
 CKT_K_G6 : OR_2 port map (A => K3, B => K4, Z => K6);
 CKT_K_G7 : OR_2 port map (A => K5, B => K6, Z => K); 
 
 -- instances and wiring for circuit L
 -- L = ABD + A'BC + A'CD + A'B'C'D'
 CKT_L_G1 : AND_3 port map (A => A, B => B, C => D, Z => L1);
 CKT_L_G2 : AND_3 port map (A => A0, B => B, C => C, Z => L2); 
 CKT_L_G3 : AND_3 port map (A => A0, B => C, C => D, Z => L3);
 CKT_L_G4 : AND_4 port map (A => A0, B => B0, C => C0, D => D0, Z => L4);
 CKT_L_G5 : OR_2 port map (A => L1, B => L2, Z => L5);
 CKT_L_G6 : OR_2 port map (A => L3, B => L4, Z => L6);
 CKT_L_G7 : OR_2 port map (A => L5, B => L6, Z => L);
 
 
 -- instances and wiring for circuit M
 CKT_M_G1 : AND_3 port map (A => A, B => C0, C => D, Z => M1);
 CKT_M_G2 : AND_3 port map (A => A0, B => B0, C => D0, Z => M2);
 CKT_M_G3 : AND_3 port map (A => A, B => B, C => D0, Z => M3);
 CKT_M_G4 : OR_2 port map (A => M1, B => M2, Z => M4);
 CKT_M_G5 : OR_2 port map (A => M3, B => M4, Z => M);
 
end;

• Bort: Do you have a test bench? You're not applying anything to your top-level ports. It would be as if you had a perfectly functional IC sitting on a tabletop, not plugged into a circuit
• Bort: I would check out tutorials on how to design stand-alone VHDL entities/components and then how to instantiate them in a test bench VHDL file. I like VHDLWhiz.com.
• Mr. Snrub: Agree with schadjo's comment, it's probably an issue with how you are instantiating your components. As you get more practice, you'll soon learn that there is rarely -- perhaps never -- a need to have components for primitive operations like AND, OR, and NOT gates. But it's still very worthwhile exercise to learn how to correctly instantiate components in your code, because you'll absolutely need them for more complex designs.

Answer 1

All wires/signals need to be set to a known state, this can be done either in a test bench or if you have memory elements then they need reset lines.

Usually in most simulations a reset is preformed at the beginning. This also needs to happen in hardware as the state of any element in the system is not known, it could be powered on to high or low, by preforming a reset we can force the system to a known state.