Strange behavior in VHDL design (randomly incrementing values)

Question

I have a fairly simple VHDL design that looks like the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity myCode is
 port (
 input_clock : in std_logic;
 do_increment : in std_logic;
 counter_out : out std_logic_vector(4 downto 0)
 );
end myCode;
architecture Behavioral of myCode is
signal internal_counter : unsigned (4 downto 0 ) := (others => '0');
signal do_increment_delay : std_logic := '0';
begin 
counter_out <= std_logic_vector(internal_counter);
process(input_clock)
begin
 if(rising_edge(input_clock)) then
 do_increment_delay <= do_increment;
 if( (do_increment = '1') and (do_increment_delay = '0') ) then
 internal_counter <= 1 + internal_counter;
 end if;
 end if;
end process;
end Behavioral;

The goal is to increment the counter_out by 1 on the rising edge of "do_increment" signal only.

When I look at my running design in ChipScope (running on Spartan-6 FPGA), I see that the code is doing what is expected:

working example

However, during periods of time when both do_increment and do_increment_delay are low, the counter begins to increase on its own:

what's going on here?!

There is no other assignment statement to counter_out anywhere.. the chipscope clock is the same one used as the input_clock to myCode. I have scoped out the do_increment physical signal into the FPGA and it is not noisy.

Any ideas?

• Elliot Alderson: You should create a testbench so you can simulate this code and probe internal signals. Make sure that you are not changing data inputs and the clock at the same time.

Answer 1

Is do_increment an external signal? If it's asynchronous to input_clock, then you should synchronize do_increment to your clock before using it in your logic.

Answer 2

I suspect noise on the do_increment line. The scope probe might be enough to suppress the noise. Does the counter increment when you are looking at the do_increment signal with the scope? You can't trust the chipscope version of do_increment because it does not come from a synchronous element clocked by the chipscope clock. As others have said, you need at least one register on the do_increment before using it in your logic. I am sure there is a warning telling you this.