vhdl "wait until" in a loop

Question

I get an error message "Error (10398): VHDL Process Statement error: Process Statement must contain only one Wait Statement" for this code
FOR i IN 0 TO N LOOP WAIT UNTIL tx_busy = '0'; tx_data <= data(i); END LOOP;
I understand what it means and why it's there, but I still feel there's a way to do what I intended, but haven't found a way

• Stack Exchange Broke The Law: FPGAs can't wait for things.
• Roman Chismar: I think they do, if it is a signal that has to get a significant value they are waiting for. For example link
• Stack Exchange Broke The Law: You can write wait, but if the compiler can figure out a way to make it not actually wait, it will do that. If it can't figure that out, you get an error. With an FPGA, all of your code is running, all of the time. You can't make code not run until something happens.
• Oldfart: In synthesis for loops are unrolled. Thus although you have written one WAIT, in fact you have N waits. Re-write using a clock and a counter for 'i'.
• user16324: Just because its legal VHDL (and does what you want in sim, which this probably won't) doesn't mean a synthesis tool has to obey it. Either find a way the tool understands, or find a better tool.

Answer 1

You loop doesn't work because loops are executed in one clock-cycle and therefore multiple WAIT-Statements exist at the same time.

This is how you could do it:

process
 variable i : natural := 0;
 constant N : natural := 42;
begin
 wait until tx_busy = '0'; -- step 1
 if i < N then -- step 2
 i := i + 1; -- |
 else -- |
 i := 0; -- |
 end if; -- |
 tx_data <= data(i); -- step 3
end process;

The code has three steps:

1. wait until tx_busy is '0'
2. increase i as long as it's smaller than N, otherwise reset it to 0
3. write out data(i) to the target signal