VHDL: How to avoid writing to and reading from 2D array at the same time?

Question

For something I work on, I must use an 2D array but I find it dangerous to write to and read from a certain memory location in the array at the same time. How can I control this situation?

When both reading and writing is necessary at the same time, I want to prioritize writing and instead of reading from that certain location, the old value should be kept in the signal to which I read from array and write.

Answer 1

You are anxious not to tell us what you are working on. Also you do not tell us if this is ASIC or FPGA nor how big the memory is.

FPGA vendors have ready-made dual-ported memories where you can set the operating mode. They all offer three modes:
1. write-before-read (This is what you are asking for?)
2. read-before-write
3. read-old, write-new

For small memories you can write your own but this website does not provide 'please write my code for me' service. You should try first and when you get stuck show us the code and where it goes wrong, then we can help you.

As last remark: I am not sure you need that behavior, mostly the read-old, write-new behavior is what is required. Alternative you find that read-write clashes doe not happen (FIFO) or double buffering is required. (e.g. BCH and FFT)

Answer 2

Reading and writing from the same memory position simultaneously is actually not a problem. If you use a dual port RAM this is exactly what you're doing.

architecture rtl of dpram is
type mem_type is array ((2** addr_width) - 1 downto 0) of
std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type;
begin
process (clk)
-- Write memory.
begin
 if (rising_edge(clk) then
 if (write_en = '1') then
 mem(conv_integer(waddr)) <= din;
 -- Using write address bus.
 end if;
 end if;
end process;
process (clk) -- Read memory.
begin
 if (rising_edge(clk)) then
 dout <= mem(conv_integer(raddr));
 -- Using read address bus.
 end if;
end process;
end rtl;

You have to take care tough in case e.g. you're storing 16bit data vectors in a 8bit Ram block. Means one dataset is split up into two cells. In this case you have to check data consistency.

• Jim Lewis: it would be better if your example used numeric_std (an IEEE standard) vs using the older std_logic_arith (an open source package provided by a vendor).
• TonyM: @JimLewis, that's an oft-quoted pov and unfortunately not substantiated. std_logic_arith has been supported and distributed by FPGA/CPLD/ASIC vendors for decades. There are mountains of designs using it and it's not going to be discarded by them, nor has it been in 30 years. It's perfectly safe and valid to use std_logic_arith.
• Jim Lewis: @TonyM: With VHDL-2008, types in numeric_std can be locally static. Not so for std_logic_arith. So you will find that there will be subtle annoying things that you cannot do with std_logic_arith.unsigned that you can do with numeric_std.unsigned. Going further, IEEE continues to work on numeric_std (as needed). Std_logic_arith has been frozen in time for at least 25 years.
• Jim Lewis: @TonyM: So really is past time for senior members of the VHDL community to commit to soft deprecating std_logic_arith - meaning do not use in new designs and examples. Support old designs as needed - but if the ports of a core level design (a block that will be reused in other designs) are a type from std_logic_arith, then the package needs to be upgraded to numeric_std as otherwise connections to numeric_std objects will be painful.
• Jim Lewis: And in this case particularly frustrating for people seeking an answer as they will not necessarily know which package this is from since there is no package reference provided.