Dealing with multiple types in VHDL

Question

I'm trying to implement this formula :

$$ output = \sum_{i=0}^{N-1} (input[i] ~~ \text{xor} ~~ input[N - i - 1]) ~~ \times ~~ 2^i $$

The input has \$ N \$ bits and the output has \$ S = N/2 \$ bits.

This is what I have:

library IEEE;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity eq is
 generic (
 N : positive := 4;
 S : positive := 2
 ); 
 port (
 I : in std_logic_vector(N-1 downto 0);
 O : out std_logic_vector(S-1 downto 0)
 );
end eq;
architecture arch of eq is 
begin
 process (I)
 variable total : integer;
 variable temp : std_logic_vector(S-1 downto 0);
 variable zeros : std_logic_vector(0 to S-2) := (others => '0');
 begin
 for k in 0 to N-1 loop
 -- do the xor operation first and store the bit at the end of an std_logic_vector of total length S
 temp := zeros & (I(k) xor I(N-k-1));
 -- multiply the above std_logic vector by 2^i, convert to integer and add to the total
 total := total + to_integer(unsigned(shift_left(unsigned(temp),k)));
 end loop;
 O <= std_logic_vector(to_unsigned(total,S));
 end process;
end arch;

I keep getting type conversion messages. It throws this on the line with total := total + ...:

Error: Near std_logic_vector ; type conversion expression type cannot be determined uniquely

When I try to fix a particular type conversion, another one pops up.

• user16324: You're importing arithmetic operators from multiple libraries including a non-standard one. So the compiler can't tell which of several + operators you really want. Stick to std_logic_1164 and numeric_std.
• user8352: Who's tool? The fourth use clause (std_logic_unsigned) is in the immediate scope of the first (numeric_std) and makes no type declarations directly visible anyway. The only directly visible type unsigned in found in numeric_std (IEEE Std 1076-2008 12. Scope and visibility, 1.2 4 Use clauses paras 7 (scope) & 8 (visibility). You appear to have discovered a bug. As Brian comments, eliminate the use clause with std_logic_unsigned, it's not used.

Answer 1

Variables are used like constants in c, not for actual signals. Stick with integer, signed, unsigned and std_logic_vector.

If you do need to translate between them then here are the functions to do that:

enter image description here

Source: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

• stanri: For the English speakers, what do the German (?) words in the image mean? Otherwise very nice diagram.