In sequential circuit block diagram, it is said that some outputs are again fed back to inputs, after storing them in memory. But, where is that memory in an SR latch? In an SR latch, it is seen that the output is directly taken to the inputs, and there is no memory.
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\$\begingroup\$ Welcome to EE.SE. There is a schematic button on the editor toolbar. It's easy to use and makes professional looking schematics to replace your Paint schematics. \$\endgroup\$Transistor– Transistor2017年10月15日 20:24:28 +00:00Commented Oct 15, 2017 at 20:24
1 Answer 1
Some of the inputs are taken from the outputs in your drawing, not the other way around. Left/Right direction in the drawing doesn't matter, signals always flow from outputs to inputs.
Since some of the inputs (one input from each NAND gate) are depending on the outputs of the NAND gates, it is sequential and with this particular configuration it has memory.