Interfacing a STM32 MCU with an external ADC (and reading the data via SPI)

Question

I want to use a STM32 microcontroller to read data from a multi-channel ADC. The microcontroller that I intend to use will most likely be something from the F7 series (such as STM32F746ZGT), whereas the ADC that I currently have my eye on is LTC2358-18 from Analog Devices.

The project that I'm working on requires me to simultaneously read 6 analog channels (with a reasonable data rate). As far as I understand, the particular ADC chip can output its conversion results on different serial data output (SDO) channels that can be read out in parallel (the serial clock is identical for all of them): enter image description here

I was wondering if it is possible to use a single STM32 MCU to read the 6 channel output data via SPI (I don't really need the two remaining channels). In general, I would assume that I need to configure 6 SPI interfaces that are available on STM32F746ZGT, as follows:

1. One of the SPIs acts as the master and provides the serial clock (SCK) for all the slave devices (5 remaining SPIs on the STM32 chip and the ADC) and the serial data out (SDO) for the ADC configuration. The master would (I'm guessing) pull down the CS for all the SPI slaves.
2. The remaining 5 SPIs on the STM32F746ZGT share a common SCK line and each are linked to a SDO channel on the ADC.

Or, in other words, it would look something like this:

enter image description here

Would this kind of configuration actually work or am I missing something?

• uhours: Is this time critical? Each SDO will output data from all channels, so you only need one SPI.
• DiBosco: What uhors says. One SPI bus and six chip selects is what is required. Unless that is too slow. However, the SPI clock speed of those ADC is proper fast so I can't see that being an issue unless I'm missing something on the ADC. A "reasonable data rate" is not a "reasonable" spec ;)
• K.R.: Well it's not too critical, but I generally want to enhance the throughput of this data acquisition system. I kinda imagined that in this kind of configuration I would be able to read the 6 channel data in (roughly) the 24 clock period. Reading the data from a single SDO would take 6 times longer. Regarding the data rate - I would prefer to achieve the 200 kSps rate that the ADC chip can offer.
• Arsenal: Interesting idea, and I can see it work. I was thinking about using the quad-SPI interface (read two values), but I'm not sure if that can be made to work like a "normal" SPI.
• K.R.: I guess I should enunciate that my main concern is that I don't know how the 1 master and 5 slave SPI interfaces will handle the time-coincident incoming data from the ADC. Can I expect all the data to be received properly on the MCU?

Answer 1

I'm no expert with STMs but for about every controller I've worked with, this wouldn't work for the following reasons:

• Probably (I didn't check) you cannot access all 6 SPI interfaces simultaneously due to pin mapping constraints, even if you use only one MISO pin from each one; I'd guess it doesn't work out.
• The six interfaces are all independent from each other, no way to sync the clock from Interface 0 to interface n. This is typically the case because the SPI peripheral is usually bought as IP, then instantiated 6 times; but there is no interconnection between those; they are separate instances with their own registers/memory regions.

What you should do instead is to read them as intended in serial (typically this is done through a DMA read). Since there is only one ADC inside and the maximum sampling rate according to the datasheet is 200k (8ch), assuming a 24 bit transfer (not sure if the STM's DMA can handle this) results in about 40 MBit data rate / spi speed. This should be possible, not accounting for post processing.

• K.R.: 1) It is physically possible to utilize all the SPIs on the STM32F746ZGT (it's a relatively big 144-pin chip). 2) The SCK synchronization between the SPIs would not be internal. All the SPIn_SCK pins would be wired together externally (together with the ADC) and the master SPI (SPI1) would be the one that provides the clock for the entire bus. I would imagine that the SPI slaves should adhere to the particular clock signal.
• 0___________: I used to do it. One master and many slaves on one micro. Slaves were clocked from the master on the same chip. This transfer is nothing for stm32
• Tom L.: @laptop2d: Thanks for correcting my 4.5MBit. I had assumed that the combined sample rate was 200kSps, not for each channel.
• Tom L.: @PeterJ: Can you state which controller you used?
• Tom L.: @K.R.: The last part is where I think you're wrong, yet I haven't tested it.

Answer 2

Your STM Processor is not multimthreaded, dont forget. You cannot physically read 6 lines in parallel. Only one at a time, use the Channel ID's and hook it all up to one line. The ADC conversion is what takes the longest in the process. Command the ADC's to convert and then read the outputs individually. Put all the them on that same line, then say 'line 1 give me data', now 'line 2 give me data', one by one. This is why Channel ID's exist, else they would be wasting valuable bits.

• K.R.: I am aware that the STM MCU is not multi-threaded. It's not too hard to read out the eight channel data via a single SDO line (as uhours mentioned in a comment above) or to read them out one-by-one. What interests me the most is how would such SPI arrangement work? Would the MCU receive data only from one SPI channel and the others would be ignored?
• 0___________: @sidA30 DMA + well managed DMA interrupts
• Voltage Spike: You can read 6 sdo lines in parallel, I do it all the time.
• user160063: I'm sure you can, but not in this application. - The ADC has a buffer, so it will hold the data for you, just tell the ADC to run and get DATA from all the lines you want it to, then once its done converting, read from all the lines individually, one by one. Your data line input will easily be fast enough to take 6 - 18 bit inputs in between each conversion cycle.