SystemVerilog module instantiation with non-existent parameter

Question

I am instantiating a module in SystemVerilog that has a lot of parameters. One of them (this is actually someone else's code) does not exist in the module definition. What will the compiler do in this case? Does it just ignore the non-existent parameter?

Here's what I mean:

Module definition:

module DummySystemVerilogModule 
# (
parameter parameter0 = 64'd0,
...
parameter parameter999 = 64'd999
) (
input wire port0,
output wire port1 )
[Body of module]
endmodule

Instantiation:

DummySystemVerilogModule # (
.parameter0 (parameter0value),
...
.parameter999 (parameter999value),
.nonexistentparameter (.nonexistentparametervalue)
) (
.port0 (wire0),
.port1 (wire1)
);

Will the compiler simply ignore the nonexistent parameter I accidentally added in the instantiation of the module?

• John Jones: I did not mean to put the . in the nonexistentparameter value, but you get a what I mean.

Answer 1

You should get a compiler error if you try to reference an identifier that doesn't exist. That's true for a parameter, port, argument, etc.