VHDL read bit from input problem

Question

entity TestRun01 is
 Port ( Clk : in STD_LOGIC;
 Din : in STD_LOGIC;
 Dout : out STD_LOGIC_vector(11 downto 0));
end TestRun01;
architecture Behavioral of TestRun01 is
 signal regr : std_logic_vector(11 downto 0) :="000000000010"; 
 signal reg : std_logic;
begin
 process(Clk,reg)
 begin
 if falling_edge(CLK) then
 if Din ='1' then
 reg <='1';
 elsif Din='0' then
 reg <='0';
 else
 reg <= reg;
 end if;
 regr(0)<=reg; 
 regr<=regr(10 downto 0) & '0';
 end if;
 end process;
 Dout<=regr;
end Behavioral;

why only shift '0' to the shift register?

why only shift '0' to the shift register?

if I change the code from

regr(0)<=reg; 
regr<=regr(10 downto 0) & '0';

to

regr<=regr(10 downto 0) & '0';
regr(0)<=reg;

the bench mark shows enter image description here

• JHBonarius: process(Clk,reg): reg is not required: the fully synchronous process only has to trigger on Clk

Answer 1

Looking at the following two lines of code:

regr(0)<=reg; 
regr<=regr(10 downto 0) & '0';

Since regr has a width of 12 bits, the second line assigns every bit in this signal. Since the last assignment to a particular signal takes priority, your initial assignment to regr(0) is effectively ignored.

In the second example with the two lines swapped, the last assignment to regr(0)<=reg; takes priority over the assignment to '0' on the previous line.

The more readable version would look like this:

regr <= regr(10 downto 0) & reg;

thus performing the whole assignment in one line without potential for confusion.

In your second example, you are seeing 'U' being shifted through, because your signal reg is not initialised. You could initialise your signal to '0' using:

signal reg : std_logic := '0'

• Yuan Cao: Thanks for your help! why the last assignment to a particular signal takes priority?
• TonyM: @YuanCao, it is part of the VHDL standard that the final assignment in a succession of assignments to a single destination takes priority.
• user8352: IEEE Std 1076-2008 10.5.2.2 Executing a simple assignment statement. See paragraph 8 rules 1) thru 5). Not so much 'takes priority' as deletes the old transactions from the projected output waveform.