single-cycle design using and shared memory for both data and instruction

Question

This is not really a question on electronics , it's more a question on logical design.
I hope this is the right place to ask.

How come it is not possible two use a single-cycle design and have a single memory for both data and instructions ?

I mean , why it is not possible to access that single memory with the address we find in the pc and then access it again using the address we find in the instruction ?

Thanks

Answer 1

Your question is making some assumptions it shouldn't. However, you have answered this yourself in large part.

In general a memory can do one access at a time. Since fetching the instruction and fetching the operand are two separate accesses at two separate addresses, they must be done sequentially with traditional memories. Even if not, the instruction has to be fetched first before you know that the operation requires a data fetch and then at what address. The logical sequence is inherently sequential.

That said, there are various speedup techniques beyond the conceptually simple scheme of a traditional processor. It would be too long to get into them here, but three that immediately come to mind are caching, pipelining, and separate instruction and data memories. All these are used to various extents in current mainstream products. Real modern processors are no longer as simple as what you are assuming in your question.

For example, most small microcontrollers use a harvard architecture, which means separate instruction and data memories. They can to simultaneous accesses since they are separate memories. However, there is still the issue of having to fetch and decode the instruction before knowing what, if anything, needs to be read from or written to data memory. This is usually dealt with to various extents with pipelining, pre-fetching, and other techniques.

I can't reproduce a whole college level course on computer architecture here, but hopefully I've given you enough keywords so that you can find lots more information on your own.

• gion: and what if we have a memory with two read ports ?
• Olin Lathrop: There are such things as "dual ported memories", but sometimes those are just carefully sequenced accesses under the hood. In any case, you still have the problem of needing to decode the instruction before knowing what data accesses may be required.
• Wouter van Ooijen: Dual ported memories are a lot more complex than standard single ported. So much that they are used (almost?) exclusively to implement CPU registers. In other situations it is much more effective to dedicate the required silicon area to makeing the memory larger.
• supercat: It may be worthwhile to note that if one implements memories using flip flops and multiplexers, adding more read ports just means adding more multiplexers, but most practical memory devices use various tricks to make memory bits a lot smaller than flip flops. Dual-ported memories have to have a different layout which may take more or less than twice the space of single-ported (I would guess probably less than twice the space for a RAM which can accommodate either two reads or one write, but more than twice the space for one which can accommodate two reads or a read and write).