Asynchronous sequential circuit - state table reduction

Question

Welcome! I got trouble in assignment like this (I got stuck):

Solve using the optimal number of rows in reduced program table. Use sr flip-flops to implement the circuit.

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I got stuck in part where I should reduce state table. I can't get it and also I can't understand things like race, so I can't solve this task.

Could you explain it to me in simple words?

My started solution is:

1) find how many states are in (completed)

2) draw state table (completed)

3) fill state table (completed)

4) reduce state table (?)

5) reduce as Moore or Mealy machine (?)

6) what next? (?)

7) get K-maps? (?)

8) draw circuits from boolean functions (?)

Solution:

State table:

state table

Filled state table (stable states are in circle):

filled state table

Any hints in simple words how to solve this exercise?

• John: The subject title is wrong - it is a synchronous state machine, not an asynchronous circuit.

Answer 1

reduce state table (?)

To reduce the state table you need to find two or more equivalent states

X and Y are equivalent if:

• All the input combinations in X and Y will lead to transition to equal states
• X and Y have the same output

Then remove any of X or Y if they are equivalent states. Removing equivalent states might lowers the number of bits required to represent all the states of your FSM in your case you need 4 bits to represent all the states of your FSM

I cant find equivalent states in the table you provided but maybe i`m wrong

reduce as Moore or Mealy machine (?)

Honestly i have no idea what does reduce as means, but this is a Moore machine since the circuit outputs does not depend on the inputs A and B instead it depends on the current state

what next? (?)

Just keep reminding yourself that this is just FSM, and all the FSMs looks the same

enter image description here

Your target is to build a combinational circuit that takes 4-bits[Current state] + 2-bits [Inputs a and b] total of 6-bits as input and the circuit output will be 4-bits [Next state] + 2-bits[X and Y] total of 6-bits as output.

A snapshot of the required truth-table might look like this

enter image description here

• A,B represents the 2-bit inputs
• C,DE,F represents the 4-bit current state inputs
• G,H are 2-bit outputs [X and Y]
• I,J,K,L represents the next state 4-bit outputs

This represents this part of the state table

enter image description here

get K-maps? (?)

draw circuits from boolean functions (?)

You will build K-map from the truth-table for every output in the circuit [Total of 6-Kmaps] then draw the required circuit. But keep in mind, the used registers will be SR flip flops this means you need some logic circuit between the next state output and the S-R f/f to make sure that the values are stored correctly