Timing loop in finite state machine sync

Question

I'm creating a FSM in VHDL to implement a serial transmission module. However, whenever I synthesize it, it throws a bunch of the same error about finding a timing loop.

[Synth 8-295] found timing loop. 

However, the line it points to looks like this:

sync_proc : process (sys_clk, sys_rst, NS) 
begin
 if (sys_rst = '1') then
 PS <= FSM_RESET;
 elsif rising_edge(sys_clk) then
 PS <= NS;
 end if;
end process sync_proc;

Specifically, the error points to the "PS <= NS" line. From what I've been taught and read in VHDL standards, this is a standard way to implement the synchronous part of an FSM, but I can't find why its giving me an issue about it now. Any thoughts?

• Paebbels: This code shows not the complete (timing) loop. Please follow the signal assignments in your code. Normally, Vivado should print the complete loop: See this example.
• user8352: With respect to Paebbels example show us the process or concurrent statement(s) assigning NS and declarations and any signals NS depends on.

Answer 1

The problem is because you included NS in your sensitivity list. The first line shall look like this

sync_proc : process (sys_clk, sys_rst) 

• David Quiñones: That's right! Another cuestión. Why do you use an asynchronous reset? It's really recomendable use synchronous reset.
• Claudio Avi Chami: I use asynchronous reset on assertion and I synchronize it for de-assertion.